2.5Gbps Single Mode SFF LC Transceiver (IR1)
C-13-2500/C-FDFB-SLC2
Features
• Duplex LC Single Mode Transceiver
• Small Form Factor Multi-sourced 2x5 Pin Package
• 1310nm, DFB Laser
• SONET /SDH STM-16 Compliant
• Single +3.3V Power Supply
• LVPECL/CML Differential level Inputs and Outputs
• LVTTL or LVPECL logic level signal-detect output choice
(C-13-2500-FDFB-SLC for LVPECL and C-13-2500C-FDFB-SLC for LVTTL)
• LVTTL disable input
• Temperature Range: 0 to 70º C
• Class 1 Laser International Safety Standard IEC 825 Compliant
• Complies with Bell Core TA-NWT-000983
General Operating
Parameter
Supply Voltage
Total Current
Inrush Current
Power Supply Noise Rejection
a
Operating Temperature (case)
Storage Temperature
Data Rate OC48/STM-16
a) 20Hz to 155MHz
Symbol
V
cc
I
cc
I
cc
'
T
op
T
st
DR
Min
3.135
Typical
3.3
Max
3.465
300
30
Unit
V
mA
mA
mV
p-p
ºC
ºC
Mb/s
100
0
-40
2488
70
85
Transmitter Specifications
Parameter
Optical Power
Average Launch power of off Tx
Extinction Ratio (dynamic)
Eye Mask
Optical Jitter generation
Optical Rise time
b
Optical Fall time
b
Mean Wavelength
Maximum RMS width (s)
Relative Intensity Noise
b) 20%-80% values
Symbol
P
op
P
off
ER
Jgen
t
r
t
f
λ
∆λ
RIN
Min
-5
8.2
Typical
Max
0
-30
Unit
dBm
dBm
dB
SONET/SDH compliant
0.002
130
130
1260
1310
1360
1
-120
UI
ps
ps
nm
nm
dB/Hz
Transmitter Electrical
Parameter
Input Differential
PECL Single Ended data input swing
PECL Differential data input swing
TxFault_Fault
TxFault_Normal
TxDisable_Disable
TxDisable_Enable
Symbol
R
in
V
in
V
in
V
fault
V
normal
V
d
V
en
Min
80
200
400
2
V
ee
2
V
ee
Typical
100
Max
120
800
1600
V
cc
0.8
V
cc
V
ee
+0.8
Unit
Ohm
mV
p-p
mV
p-p
V
V
V
V
2.5Gbps Single Mode SFF LC Transceiver (IR1)
C-13-2500/C-FDFB-SLC2
Receiver Specifications
Parameter
Receive Power Low
d
Receive Power High
Damage Threshold for Receiver
Wavelength
LOS Assert
LOS De-assert
LOS hysteresis
d) at 10
-10
BER, PRBS 2
23
-1
Electrical Output
Parameter
PECL Single ended data output swing
PECL Differential data output swing
Data output rise time
Data output fall time
Symbol
R
sens,low
R
sens,high
P
in,damage
λ
Min
Typical
-20
1100
-28
1
Max
-18
0
0
1600
-18
Unit
dBm
dBm
dBm
nm
dBm
dBm
dB
Symbol
V
out
V
out
T
r
T
f
Min
250
500
Typical
Max
500
1000
Unit
mV
p-p
mV
p-p
ps
ps
130
130
Timing and Electrical
Parameter
Tx Disable Negate time
Tx Disable assert time
Time to initialize, including reset of TX fault
Tx fault Assert time
Tx Disable to reset
LOS Assert time
LOS De-assert time
Serial ID Clock Rate
RX_LOS Voltage (high)
RX_LOS Voltage (low)
LOS output voltage-Fault
LOS output voltage-Normal
MOD_DEF (0:2)-High
MOD_DEF (0:2)-Low
Symbol
t_on
t_off
t_init
t_fault
t_reset
t_loss_on
t_loss_off
f_serial_clock
Min
Typical
Max
1
10
300
100
Unit
ms
µs
ms
µs
µs
µs
µs
KHz
V
V
V
V
V
V
10
100
100
100
2
V
ee
+0.3
0.8
V
cc
V
ee
+0.3
V
cc
V
ee
+0.3
0
2
V
ee
2
V
ee
V
LOS
fault
V
LOS
normal
V
h
V
l
2.5Gbps Single Mode SFF LC Transceiver (IR1)
C-13-2500/C-FDFB-SLC2
Outline Drawing
Pinout Definitions
Pin
1
2
3
4
5
6
7
8
9
10
Symbol
RxGND
RxVcc
SD
RD-
RD+
TxVcc
TxGND
TxDIS
TD+
TD-
v
Notes
Directly connect this pin to the receiver ground plane
+3.3V dc power for the receiver section
Active high on this indicates a received optical signal (LVTTL or LVPECL)
Receiver Data out Bar(LVPECL/CML)
Receiver Data out (LVPECL/CML)
+3.3V dc power for the transmitter section
Directly connect this pin to the transmitter ground plane
Transmitter disable (LVTTL)
Transmitter Data In (LVPECL/CML)
Transmitter Data In Bar (LVPECL/CML)
Attaching Posts
The attaching posts are at the case potential and may be connected
chassis ground. They are not isolated from circuit ground.
Recommended Circuit Schematics
Inputs to the C-1x-2500/C-Fx-SLCx series transmitters are AC coupled and internally terminated through 50 ohm to AC ground. These
transceivers can operate with LVPECL or CML logic levels. The input signal must have at least a 200 mV peak to peak (single ended) signal
swing. Output from the receiver section of the module is also AC coupled and is expected to drive into 50 ohm load. Different termination
strategies may be required depending on the particular Serializer/Deserializer chip set used. The C-1x-2500/C-Fx-SLCx series product family
are designed with AC coupled data inputs and outputs to provide the following a advantages:
• Close positioning of SERDES with respect to transceiver; allow for shorter line lengths and at gigabit speeds reduces EMI.
• Mininum number of external components.
• Internal termination reduces the potential for unterminated stubs which would otherwise increase jitter and reduce
transmission margin.
Figure 1 & 2 illustrates the recommended transmit and receive data line terminations for SERDES with CML and LVPECL Inputs/outputs
respectively.
2.5Gbps Single Mode SFF LC Transceiver (IR1)
C-13-2500/C-FDFB-SLC2
TX_ DI S
8
TTL l ogic level
TX_ GND 7
Z=50!
MI TTE R
DR IV E R
TX _D 9
TD
+
TX _D 10
R
Z=50!
TD
-
LA SE
Vc c_T X
V cc_RX
6
2
3
See
Fig. 4A
See
Fi g. 3
Z=50!
S
w
erializer / De-S erializer
ith CML lnputs/Outputs
SD
RX _D
POST
AMP
BIAS
TZ
AMP
4
RD
RX _D
Z=50!
5
1
RD
-
R X _GND
+
Note 1
ER
Figure 1. Recommended TRANSMIT adn RECEIVE Data Termination for SERDES with CML I/Os
Note 1. Consult SERDES manufacurer's data sheet and application data for appropriate receiver iput biasing network.
Some deserializer inputs are internally termintated and may not need external termination resistors.
TX_DI S
8
T T L logic le ve l
TX_ GND 7
TR AN SM IT T E R
Z=50!
TX _D 9
DR I V E R
TD +
TX_ D 10
LA SE R
Z=50!
TD -
V cc_T X
Vc c_R X
6
2
3
See
F ig. 4A
See
Fi g. 3
Z=50!
13 0
Note 1
Ser ializ er / De- S eria liz e r
with LV P E C L lnpu ts/Outputs
Vc c = + 3 .3 V
13 0
SD
BI AS
RX _D
PI N
TZ
AMP
PO ST
AM P
4
RD -
RX _D
R X _GND
Z=50!
5
1
RD +
RE CE I V E R
Figure 2. Recommended TRANSMIT and RECEIVE Data Terminations for SERDES with LV PECL I/Os.
Note 1. Consult SERDES manufacurer's data sheet and application data for appropriate receiver iput biasing
network. Some deserializer inputs are internally termintated and may not need external termination resistors.
2.5Gbps Single Mode SFF LC Transceiver (IR1)
C-13-2500/C-FDFB-SLC2
SIGNAL DETECT
The C-13-2500-F-SLC/C-13-2500C-F-SLC
transceivers are equipped with LVTTL / LVPECL
signal detect outputs. The standard LVTTL
output eliminates the need for a LVPECL to
LVTTL level shifter in most applications.
LVPECL
or
LVTTL Logic
R: For LVTTL leve l R= 100k or N.C
LVPECL level R= 510
Figure 3: Signal Detect
POWER COUPLING
A suggested layout for power and
ground connections is given in figure
4B below. Connections are made via
separate voltage and ground planes.
The mounting posts are at case ground
and should not be connected to circuit
ground. The mounting posts are at
case gound and should not be
connected to circuit ground. The ferrite
gead should provide a real impedance
of 50 to 100 ohms at 100 to
1000MHz. Bypass capacitors should
be placed as close to the 10-pin
connector as possible.
Ac c
L1
C3
C1
C2
C4
VA LUES:
C 1, C 2 = 1000p F,
C 3, = 0.1 u F
C 4, = 10 uF,
L1, L2 = R e a l im p e d n c e o f 50 to
100 O hm s to 1000 MHz.
F igure 4A: Suggested er Coupling-Electrical Schematic
Pow
L1
C2
TOP VI EW
C3 C4
C1
L2
VA LUES:
C 1, C 2 = 1000p F,
C 3,
= 0.1uF
C 4,
= 10uF,
L1, L2 = Re a l im p e d a nc e of 50 to
100 O hms to 1000MHz.
NO TE :
1.) Com p o nent s shown ore p la c ed
on t he b o ttom la yer a nd a re
v ie we d throug h the b oard .
LEHEND:
Vc c PL ANE C O NN EC TION
F igure 4B: Suggest Pow Coupling-Com
ed
er
ponent P
lacement
!
!
CIRCUIT GRO UND PLA NE CO NNEC TION
CA SE GRO UND
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