XC6118
Series
Voltage Detector with Separated Sense Pin & Delay Capacitor Pin
ETR0213-004
■GENERAL
DESCRIPTION
The XC6118 series is a low power consumption voltage detector with high accuracy detection, manufactured using CMOS
process and laser trimming technologies.
Since the sense pin is separated from the power supply pin, it allows the IC to monitor the other power supply.
The XC6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0V.
Moreover, a release delay time can be adjusted by the external capacitor connected to the Cd pin.
The V
OUT
pin is available in both CMOS and N-channel open drain output configurations.
■APPLICATIONS
●Microprocessor
reset circuitry
●Charge
voltage monitors
●Memory
battery back-up switch circuits
●Power
failure detection circuits
■FEATURES
:±2％(Detect Voltage≧1.5V)
:±30mV(Detect Voltage＜1.5V)
Low Power Consumption
: 0.4μA(Detect, V
IN
=1.0V) (TYP.)
: 0.8μA(Release, V
IN
=1.0V)(TYP.)
Detect Voltage Range
: 0.8V½5.0V (0.1V increments)
Operating Voltage Range
: 1.0V½6.0V
Temperature Characteristics
:
±100ppm/℃(TYP.)
Output Configuration
: CMOS, N-channel open drain
Operating Temperature Range
: -40℃½+85℃
Separated Sense Pin
: Power supply separation
Built-in delay time
: Release delay time adjustable
Packages
: USP-4, SOT-25
Environmentally Friendly
: EU RoHS Compliant, Pb Free
High Accuracy
■TYPICAL
APPLICATION CIRCUIT
■TYPICAL
PERFORMANCE
CHARACTERISTICS
●Output
Voltage vs. Sense Voltage
XC6118C25AGR
Ta=25
℃
Output Voltage: VOUT (V)
Monitering
Power
別電源
supply
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
0
1
2
3
4
5
6
1.0V
4.0V
VIN=6.0V
(No Pull-Up resistor needed for
CMOS output product)
Sense Voltage: VSEN (V)
1/20
XC6118
Series
■PIN
CONFIGURATION
Cd/NC
2
5
VSS
3 VSEN
4
VIN
VOUT 1
USP-4
（BOTTOM
VIEW）
* In the XC6118xxxA/B series, the dissipation pad
should not be short-circuited with other pins.
* In the XC6118xxxC/D series, when the dissipation
pad is short-circuited with other pins, connect it to
the NC pin (No.2) pin before use.
SOT-25
（TOP
VIEW）
■PIN
ASSIGNMENT
PIN NUMBER
USP-4
SOT-25
1
2
2
3
4
5
1
5
-
4
3
2
PIN NAME
V
OUT
Cd
NC
V
SEN
V
IN
V
SS
FUNCTION
Output (Detect ”L”)
Delay Capacitance
(*1)
No Connection
Sense
Input
Ground
(*2)
NOTE:
*1: With the V
SS
pin of the USP-4 package, a tab on the backside is used as the pin No.5.
*2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will
be used as the NC.
■PRODUCT
CLASSIFICATION
●Ordering
Information
XC6118①②③④⑤⑥-⑦
(*1)
DESIGNATOR
①
②③
DESCRIPTION
Output Configuration
Detect Voltage
SYMBOL
C
N
08~50
A
B
④
Options
C
D
⑤⑥-⑦
Packages
Taping Type
(*2)
GR-G
MR-G
CMOS output
N-ch open drain output
e.g. 18
→
1.8V
Built-in delay capacitance pin, hysteresis 5% (TYP.)(Standard*)
Built-in delay capacitance pin, hysteresis less than 1%(Standard*)
No built-in delay capacitance pin, hysteresis 5% (TYP.)
(Semi-custom)
No built-in delay capacitance pin, hysteresis less than 1%
(Semi-custom)
USP-4 (Halogen & Antimony free)
SOT-25 (Halogen & Antimony free)
DESCRIPTION
*When delay function isn’t used, open the delay capacitance pin before use.
(*1)
(*2)
The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
The device orientation is fixed in its embossed tape pocket.
For reverse orientation, please contact your local Torex sales office or representative.
(Standard orientation:
⑤R-⑦,
Reverse orientation:
⑤L-⑦)
2/20
XC6118
Series
■BLOCK
DIAGRAMS
(1)
XC6118CxxA
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118CxxC (semi-custom).
(2)
XC6118CxxB
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118CxxD (semi-custom).
(3)
XC6118NxxA
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118NxxC (semi-custom).
(4)
XC6118NxxB
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118NxxD (semi-custom).
3/20
XC6118
Series
■ABSOLUTE
MAXIMUM RATINGS
●XC6118xxxA/B
PARAMETER
Input Voltage
Output Current
XC6118C
(*1)
Output Voltage
XC6118N
(*2)
Sense Pin Voltage
Delay Capacitance Pin Voltage
Delay Capacitance Pin Current
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
SYMBOL
V
IN
I
OUT
V
OUT
V
SEN
V
CD
I
CD
Pd
Ta
Tstg
RATINGS
V
SS
-0.3½7.0
10
V
SS
-0.3½V
IN
+0.3
V
SS
-0.3½7.0
V
SS
-0.3½7.0
V
SS
-0.3½V
IN
+0.3
5.0
120
250
-40½+85
-55½+125
Ta=25℃
UNITS
V
mA
V
V
V
mA
mW
o
o
C
C
●XC6118xxxC/D
PARAMETER
Input Voltage
Output Current
XC6118C
(*1)
Output Voltage
(*2)
XC6118N
Sense Pin Voltage
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
NOTE:
*1: CMOS output
*2: N-ch open drain output
Ta=25℃
SYMBOL
V
IN
I
OUT
V
OUT
V
SEN
Pd
Ta
Tstg
RATINGS
V
SS
-0.3½7.0
10
V
SS
-0.3½V
IN
+0.3
V
SS
-0.3½7.0
V
SS
-0.3½7.0
120
250
-40½+85
-55½+125
UNITS
V
mA
V
V
mW
o
o
C
C
4/20
XC6118
Series
■ELECTRICAL
CHARACTERISTICS
●XC6118xxxA
PARAMETER
Operating Voltage
Detect Voltage
Hysteresis Width
Detect Voltage
Line Regulation
Supply Current 1
(*2)
Ta=25℃
SYMBOL
V
IN
V
DF
V
HYS
ΔV
DF
/
(ΔV
IN
・V
DF
)
I
SS1
CONDITIONS
V
DF(T)
=0.8½5.0V
V
IN
=1.0½6.0V
V
IN
=1.0½6.0V
V
IN
=1.0½6.0V
V
SEN
=V
DF
×0.9
V
IN
=1.0V
V
IN
=6.0V
V
SEN
=V
DF
×1.1
0.4
0.4
0.8
0.9
0.1
0.8
1.2
1.6
1.8
1.9
0.7
1.6
2.0
2.3
2.4
2.5
mA
③
1.0
1.0
1.6
1.8
μA
②
μA
②
(*1)
MIN.
1.0
TYP.
MAX.
6.0
UNITS
V
V
V
%/V
CIRCUITS
-
①
①
①
E-1
E-2
±0.1
Supply Current 2
(*2)
I
SS2
V
IN
=1.0V
V
IN
=6.0V
V
SEN
=0V, V
DS
=0.5V(Nch)
V
IN
=1.0V
V
IN
=2.0V
I
OUT1
Output Current
(*3)
V
IN
=3.0V
V
IN
=4.0V
V
IN
=5.0V
V
IN
=6.0V
V
SEN
=6.0V,
V
DS
=0.5V(Pch)
V
IN
=1.0V
V
IN
=6.0V
I
OUT2
-0.30
-1.00
-0.08
-0.70
mA
④
Leakage
Current
CMOS Output
I
LEAK
N-ch Open Drain
Output
ΔV
DF
/
(ΔT
opr
・V
DF
)
R
SEN
R
DELAY
I
CD
V
TCD
V
UNS
t
DF0
t
DR0
V
IN
=6.0V, V
SEN
=6.0V,
V
OUT
=6.0V, Cd: Open
0.20
μA
0.20
0.40
③
Temperature Characteristics
(*4)
-40 C≦T
a
≦85
C
V
SEN
=5.0V V
IN
=0V
V
SEN
=6.0V V
IN
=5.0V
Cd=0V
Cd=0.5V, V
IN
=1.0V
V
SEN
=6.0V V
IN
=1.0V
V
SEN
=6.0V V
IN
=6.0V
V
IN
=V
SEN
=0½1.0V
V
IN
=6.0V, V
SEN
=6.0→0V
Cd: Open
V
IN
=6.0V, V
SEN
=0→6.0V
Cd: Open
0.4
2.9
1.6
o
o
±100
ppm/ C
o
①
⑤
⑥
⑥
⑦
⑧
⑨
⑨
Sense Resistance
Delay Resistance
E-4
2.0
200
0.5
3.0
0.3
30
30
0.6
3.1
0.4
230
200
2.4
MΩ
MΩ
μA
V
V
μs
μs
(*5)
Delay capacitance pin
Sink Current
Delay Capacitance Pin Threshold
Voltage
Undefined Operation
Detect Delay Time
(*6)
(*7)
Release Delay Time
(*8)
NOTE:
*1: V
DF (T)
: Nominal detect voltage
*2: Current to the sense resistor is not included.
*3: I
OUT2
is applied only to the XC6118C series (CMOS output).
*4: It is calculated from the voltage value and the current value of the V
SEN
.
*5: It is calculated from the voltage value of the V
IN
and the current value of the Cd.
*6: Maximum V
OUT
voltage when V
IN
is changed from 0V to 1.0V under connecting the V
IN
pin to the V
SEN
pin.
This value is effective only to the XC6118C series (CMOS output).
*7: Delay time from the time of V
SEN
=V
DF
to the time of V
OUT
= 0.6V when the V
SEN
falls.
*8: Delay time from the time of V
IN
= V
DF
+V
HYS
to the time of V
OUT
= 5.4V when the V
SEN
rises.
5/20
嵌入式系统
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