MC68HC908MR32/D
REV 5
68HC08M6
HC08M68H
8M68HC08
MC68HC908MR32
MC68HC908MR16
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HCMOS
Microcontroller Unit
MC68HC908MR32
MC68HC908MR16
Technical Summary
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herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
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disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
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Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2001
MC68HC908MR16/MC68HC908MR32 — Rev. 5.0
MOTOROLA
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3
Revision History
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Figure 2-1. Memory Map
— Added FLASH Block Protect Register
(FLBPR) at address location $FF7E
3
Figure A-1. MC68HC908MR16 Memory Map
— Added FLASH Block
Protect Register (FLBPR) at address location $FF7E
4
19.4.3 Conversion Time
— Reworked equations and text for clarity.
Figure 10-1. Monitor Mode Circuit
— PTA7 and connecting circuitry
added
Table 10-2. Monitor Mode Signal Requirements and Options
— Switch
locations added to column headings for clarity
5
Section 11. Timer Interface A (TIMA)
— Timer discrepancies corrected
throughout this section.
Section 12. Timer Interface B (TIMB)
— Timer discrepancies corrected
throughout this section.
199
225
388
346
187
189
Page
Number(s)
41
August,
2001
October,
2001
December,
2001
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4
MC68HC908MR16/MC68HC908MR32 — Rev. 5.0
MOTOROLA
Advance Information — MC68HC908MR16/MC68HC908MR32
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 55
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 57
Section 5. Configuration Register (CONFIG) . . . . . . . . . 67
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 71
Section 7. System Integration Module (SIM) . . . . . . . . . 89
Section 8. Clock Generator Module (CGM) . . . . . . . . . . 109
Section 9. Pulse-Width Modulator
for Motor Control (PWMMC) . . . . . . . . . . . 135
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 185
Section 11. Timer Interface A (TIMA). . . . . . . . . . . . . . . 199
Section 12. Timer Interface B (TIMB). . . . . . . . . . . . . . . 225
Section 13. Serial Peripheral Interface Module (SPI) . . 249
Section 14. Serial Communications Interface
Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 279
Section 15. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 309
Section 16. Computer Operating Properly (COP) . . . . 325
Section 17. External Interrupt (IRQ) . . . . . . . . . . . . . . . 331
MC68HC908MR16/MC68HC908MR32 — Rev. 5.0
MOTOROLA
List of Sections
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