Advanced
CAT25C03/05/09/17/33
2K/4K/8K/16K/32K SPI Serial CMOS E
2
PROM
FEATURES
s
10 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Zero Standby Current
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)
s
Commercial, Industrial and Automotive
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
s
8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
s
Page Write Buffer
s
Write Protection
Temperature Ranges
– Protect First Page, Last Page, Any 1/4 Array
or Lower 1/2 Array
DESCRIPTION
The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit
SPI Serial CMOS E
2
PROM internally organized as
256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C03/05 features a
16-byte page write buffer. The 25C09/17/33 features a
32-byte page write buffer.The device operates via the
SPI bus serial interface and is enabled though a Chip
Select (CS). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The
HOLD
pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C03/05/09/17/33 is de-
signed with software and hardware write protection
features. The device is available in 8-pin DIP, 8-pin
SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP
packages.
PIN CONFIGURATION
TSSOP Package (U14) SOIC Package (S16) SOIC Package (S) DIP Package (P)
CS
SO
NC
NC
NC
WP
V
SS
TSSOP Package (U)
1
2
3
4
8
7
6
5
VCC
HOLD
SCL
SI
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
CS
SO
NC
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
CS
HOLD
SO
SCK
WP
SI
VSS
1
2
3
4
8
7
6
5
VCC
CS
HOLD
SO
SCK
SI
WP
VSS
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
NC
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
E
2
PROM
ARRAY
DATA IN
STORAGE
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25068-00 2/98
CAT25C03/05/09/17/33
Advanced
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL(3)
V
IH(3)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
5
0.4
0
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
4.5V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 25068-00 2/98
2
Advanced
CAT25C03/05/09/17/33
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
V
V
OH
t
HO
t
DIS
HI-Z
SO
V
OL
HI-Z
A.C. CHARACTERISTICS
Limits
1.8, 2.5
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
HOLD Time
Write Cycle Time
Output Valid from Clock Low
Output HOLD Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
HOLD Time
250
250
250
0
250
100
100
100
100
100
100
10
200
0
75
50
Min.
50
50
200
200
DC
2
50
2
2
40
40
5
80
Max.
4.5V-5.5V
Min.
10
20
40
40
DC
10
50
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
C
L
= 100pF
C
L
= 50pF
Test
UNITS Conditions
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 25068-00 2/98
CAT25C03/05/09/17/33
Advanced
FUNCTIONAL DESCRIPTION
The CAT25C03/05/09/17/33 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C03/05/09/17/33 to
interface directly with many of today’s popular
microcontrollers. The CAT25C03/05/09/17/33 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
and the 25C03/05/09/17/33. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK.
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C03/
05/09/17/33 and
CS
high disables the CAT25C03/05/
09/17/33.
CS
high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C03/05/09/17/33 draws ZERO current in the
Standby mode. A high to low transition on
CS
is required
prior to any sequence being initiated. A low to high
transition on
CS
after a valid write sequence is what
initiates an internal write cycle.
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low, all write operations to the device
are inhibited.
WP
going low while
CS
is still low will
interrupt a write to the status register. If the internal write
cycle has already been initiated,
WP
going low will have
no effect on any write operation to the status register.
HOLD:
HOLD
Hold
HOLD
is the HOLD pin. The
HOLD
pin is used to pause
transmission to the CAT25C03/05/09/17/33 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause,
HOLD
must be
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C03/05/09/17/33. Input data is latched on the rising
edge of the serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C03/05/09/17/33. During a
read cycle, data is shifted out on the falling edge of the
serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Max.
1
1
Units
ms
ms
Note:
(1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 25068-00 2/98
4
Advanced
CAT25C03/05/09/17/33
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,
HOLD
is brought high, while SCK is low.
(HOLD should be held high any time this function is not
being used.)
HOLD
may be tied high directly to V
CC
or
tied to V
CC
through a resistor. Figure 9 illustrates hold
timing sequence.
STATUS REGISTER
The status register defines the protection status of the
device. The register features three protection bits which
allow the user to protect the desirable part of the memory
array. There are seven different variations for the protec-
tion mechanism. The protection can vary from one page
to as much as half of the entire array. These areas and
associated address ranges are protected by configuring
the protection bits of the status register through WRSR
instruction. Once the three protection bits are set, the
associated memory can be read but not written until the
protection bits are reset.
STATUS REGISTER
7
0
6
0
5
0
4
0
3
0
2
IDL2
1
IDL1
0
IDL0
MEMORY PROTECTION
IDL2
0
0
0
0
1
1
1
1
IDL1
0
0
1
1
0
0
1
1
IDL0
0
1
0
1
0
1
0
1
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
25C03
Q1
Q2
Q3
Q4
H1
P0
Pn
00-3F
40-7F
80-BF
C0-FF
00-7F
00-0F
F0-FF
25C05
25C09
25C17
000-1FF
200-3FF
400-5FF
600-7FF
000-3FF
000-01F
25C33
000-3FF
400-7FF
800-BFF
C00-FFF
000-7FF
000-01F
000-07F 000-0FF
080-0FF 100-1FF
100-17F 200-2FF
180-1FF 300-3FF
000-0FF 000-1FF
000-00F 000-01F
1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF
5
Doc. No. 25068-00 2/98
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
