(G); 19 address inputs, A(18:0); and eight bidirectional data
lines, DQ(7:0). E1 and E2 device enables control device
selection, active, and standby modes. Asserting E1 and E2
enables the device, causes I
DD
to rise to its active value, and
decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
W
X
X
0
1
1
E2
X
0
1
1
1
E1
1
X
0
0
0
I/O Mode
3-state
3-state
Data in
3-state
Data out
Mode
Standby
Standby
Write
Read
2
Read
Figure 2. 15ns SRAM Pinout (36)
X
X
1
PIN NAMES
A(18:0)
DQ(7:0)
E1
E2
Address
Data Input/Output
Chip Enable 1
(active low)
Chip Enable 2
(active high)
W
G
WriteEnable
Output Enable
0
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1 less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of chip enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as chip enable
and output enable are active, the address inputs may change at
a rate equal to the minimum read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified t
ETQV
is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t
GLQV
unless t
AVQV
or t
ETQV
have not been
satisfied.
V
DD1
Power (1.8V)
V
DD2
Power (3.3V)
V
SS
Ground
2
WRITE CYCLE
A combination of W and E1 less than V
IL
(max) and E2 greater
than V
IH
(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either G is greater than V
IH
(min), or
when W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with E1
and E2 still active. The write pulse width is defined by t
WLWH
when the write is initiated by W, and by t
ETWH
when the write
is initiated by E1 or E2. Unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait t
WLQZ
before applying data to the nine bidirectional
pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure
4b, is defined by a write terminated by either of E1 or E2 going
inactive. The write pulse width is defined by t
WLEF
when the
write is initiated by W, and by t
ETEF
when the write is initiated
by either E1or E2 going active. For the W initiated write, unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait t
WLQZ
before applying data to
the eight bidirectional pins DQ(7:0) to avoid bus contention.
OPERATIONAL ENVIRONMENT
The UT8R512K8 SRAM incorporates special design and
layout features which allows operation in a limited
environment.
Table 2. Operational Environment
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
300K
8.9x10
-10
rad(Si)
Errors/Bit-Day
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 2.1V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
LIMITS
1.7 to 1.9V
1
3.0 to 3.6V
(P) Screening: -25°C
(C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
0V to V
DD2
V
IN
Notes:
DC input voltage
1. For increased noise immunity, supply voltage (V
DD1
) can be increased to 2.0V. If not tested, all applicable DC and AC charateristics are guaranteed by characterization
at V
DD1
(max) = 2.0V.
4
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
Unless otherwise noted, Tc is per the temperature ordered
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