CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s
Fast Read Access Times: 120/150 ns
s
Low Power CMOS Dissipation:
s
Automatic Page Write Operation:
–Active: 50 mA Max.
–Standby: 200
µ
A Max.
s
Simple Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s
End of Write Detection:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
–Toggle Bit
–DATA Polling
DATA
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial and Automotive
–5ms Max
s
CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
A7–A15
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
65,536 x 8
E
2
PROM
ARRAY
128 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5096 FHD F02
I/O0–I/O7
A0–A6
ADDR. BUFFER
& LATCHES
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1007, Rev. A
CAT28C512/513
PIN CONFIGURATION
DIP Package (P)
PLCC Package (N)
A12
A15
NC
NC
VCC
WE
NC
PLCC Package (N)
A15
VCC
WE
A7
A12
A14
A13
29
28
27
CAT28C513
TOP VIEW
26
25
24
23
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
29
28
27
26
25
24
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
4 3 2 1 32 31 30
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
CAT28C512
TOP VIEW
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
10
11
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
5096 FHD F01
TSOP Package (10mm X 14mm) (T14)
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
TSOP Package (8mmx20mm) (T)
NC
I/O3
I/O4
I/O5
CAT28C512
TOP VIEW
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CAT28C512
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN FUNCTIONS
Pin Name
A
0
–A
15
I/O
0
–I/O
7
CE
OE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Pin Name
WE
V
CC
V
SS
NC
Function
Write Enable
5V Supply
Ground
No Connect
Doc. No. 1007, Rev. A
2
CAT28C512/513
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min
100,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
±10%,
unless otherwise specified.
Limits
Symbol
I
CC
I
CCC(5)
I
SB
I
SBC(6)
I
LI
I
LO
V
IH(6)
V
IL(5)
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Operating, CMOS)
V
CC
Current (Standby, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
3.5
-10
-10
2
-1
2.4
0.4
Min
Typ
Max.
50
25
3
200
10
10
V
CC
+0.3
0.8
Units
mA
mA
mA
µA
µA
µA
V
V
V
V
V
I
OH
= –400µA
I
OL
= 2.1mA
Test Conditions
CE
=
OE
= V
IL
, f=6MH
z
All I/O’s Open
CE
=
OE
= V
ILC
, f=6MH
z
All I/O’s Open
CE
= V
IH
, All I/O’s Open
CE
= V
IHC
,
All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE
= V
IH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILC
= –0.3V to +0.3V.
(6) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
3
Doc. No. 1007, Rev . A
CAT28C512/513
MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High-Z
High-Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
A.C. CHARACTERISTICS, Read Cycle
V
CC
=5V + 10%, Unless otherwise specified
28C512/513-12 28C512/513-15
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ(1)
t
OLZ(1)
t
HZ(1)(2)
t
OHZ(1)(2)
t
OH(1)
Parameter
Read Cycle Time
CE
Access Time
Address Access Time
OE
Access Time
CE
Low to Active Output
OE
Low to Active Output
CE
High to High-Z Output
OE
High to High-Z Output
Output Hold from Address Change
0
0
0
50
50
0
Min.
120
120
120
50
0
0
50
50
Max.
Min.
150
150
150
70
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-Up Timing
Symbol
t
PUR (1)
t
PUW (2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
5
Min.
Max
100
10
Units
µs
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1007, Rev. A
4
CAT28C512/513
A.C. CHARACTERISTICS, Write Cycle
V
CC
=5V+10%, unless otherwise specified
28C512/513-12 28C512/513-15
Min. Max. Min. Max. Units
5
0
50
0
0
100
0
0
100
50
0
5
0.1
10
100
0
50
0
0
100
0
0
100
50
0
5
0.1
10
100
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW(3)
t
OES
t
OEH
t
WP(3)
t
DS
t
DH
t
INIT(1)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE
Setup Time
CE
Hold Time
CE
Pulse Time
OE
Setup Time
OE
Hold Time
WE
Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
t
BLC(1)(4)
Byte Load Cycle Time
Figure 1. A.C. Testing Input/Output Waveform(2)
2.4 V
INPUT PULSE LEVELS
0.45 V
0.8 V
5096 FHD F03
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
5096 FHD F04
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
5
Doc. No. 1007, Rev . A
FPGA/CPLD
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