CAT28F002
2 Megabit CMOS Boot Block Flash Memory
FEATURES
s
Fast Read Access Time: 90/120/150 ns
s
On-Chip Address and Data Latches
s
Blocked Architecture:
s
Electronic Signature
Licensed Intel
second source
s
100,000 Program/Erase Cycles and 10 Year
Data Retention
s
Standard Pinouts:
— One 16-KB Protected Boot Block
• Top or Bottom Locations
— Two 8-KB Parameter Blocks
— One 96-KB Main Block
— One 128-KB Main Block
s
Hardware Data Protection
s
Automated Program and Erase Algorithms
s
Automatic Power Savings Feature
s
Low Power CMOS Operation
s
12.0V
— 40-Lead TSOP
— 40-Lead PDIP
s
High Speed Programming
s
Commercial, Industrial and Automotive Tem-
perature Ranges
s
Reset/Deep PowerDown Mode
— 0.2
µ
A I
CC
Typical
— Acts as Reset for Boot Operations
±
5% Programming and Erase Voltage
DESCRIPTION
The CAT28F002 is a high speed 256K X 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F002 has a blocked architecture with one 16
KB Boot Block, two 8 KB Parameter Blocks, one 96 KB
Main Block and one 128 KB Main Block. The Boot Block
section can be at the top or bottom of the memory map.
The Boot Block section includes a reprogramming write
lock out feature to guarantee data integrity. It is de-
signed to contain secure code which will bring up the
system minimally and download code to other locations
of CAT28F002.
The CAT28F002 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F002 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms. A deep power-down mode lowers the
total V
cc
power consumption 1µw typical.
The CAT28F002 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin TSOP and 40-pin PDIP packages.
BLOCK DIAGRAM
ADDRESS
COUNTER
WRITE STATE
MACHINE
RP
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
ERASE VOLTAGE
SWITCH
I/O0–I/O7
I/O BUFFERS
STATUS
REGISTER
DATA
LATCH
COMPARATOR
ADDRESS LATCH
SENSE
AMP
CE
OE
Y-GATING
Y-DECODER
16K-BYTE BOOT BLOCK
8K-BYTE PARAMETER BLOCK
8K-BYTE PARAMETER BLOCK
96K-BYTE MAIN BLOCK
128K-BYTE MAIN BLOCK
A0–A17
VOLTAGE VERIFY
SWITCH
X-DECODER
28F002 F01
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25072-00 2/98 F-1
CAT28F002
PIN CONFIGURATION
PDIP Package (P)
NC
NC
A0
CE
GND
OE
I/O0
I/O1
I/O2
I/O3
VCC
VCC
I/O4
I/O5
I/O6
I/O7
A10
GND
A17
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
A1
A2
A3
A4
A5
A6
A7
VPP
RP
WE
A8
A9
A11
A12
A13
A14
A15
A16
NC
TSOP Package (T)
A17
GND
NC
NC
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0
A16
A15
A14
A13
A12
A11
A9
A8
WE
RP
VPP
DU
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIN FUNCTIONS
Pin Name
A
0
–A
17
I/O
0
–I/O
7
CE
OE
WE
V
CC
V
SS
V
PP
RP
DU
Input
Type
Input
I/O
Input
Input
Input
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
Power Down
Do Not Use
28F002 F03
Doc. No. 25072-00 2/98 F-1
2
CAT28F002
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
Voltage on Pin A
9
with
Respect to Ground
(1)
................... –2.0V to +13.5V
V
PP
with Respect to Ground
during Program/Erase
(1)
.............. –2.0V to +14.0V
V
CC
with Respect to Ground
(1)
............ –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz
Limits
Symbol
C
IN(3)
C
OUT(3)
C
VPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
V
PP
Supply Capacitance
Min
Max.
8
12
25
Units
pF
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
V
PP
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
3
Doc. No. 25072-00 2/98 F-1
CAT28F002
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V
±10%,
unless otherwise specified
Limits
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
PPD
I
CC1
I
CC2(1)
I
CC3(1)
I
PPS
I
PP1
I
PP2(1)
I
PP3(1)
V
IL
V
OL
V
IH
V
OH1
V
ID
I
ID
I
CCD
I
CCES
I
PPES
I
RP
V
OH2
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
PP
Deep Powerdown Current
V
CC
Active Read Current
V
CC
Programming Current
V
CC
Erase Current
V
PP
Standby Current
V
PP
Read Current
V
PP
Programming Current
V
PP
Erase Current
Input Low Level
Output Low Level
Input High Level
Output High Level TTL
A
9
Signature Voltage
A
9
Signature Current
V
CC
Deep Powerdown Current
V
CC
Erase Suspend Current
V
PP
Erase Suspend Current
RP Boot Block Unlock Current
Output High Level TTL
0.85 V
CC
2.0
2.4
10.8
13.2
500
1.0
10
200
500
–0.5
Min.
Max.
±1.0
±10
100
1.5
5.0
55
50
30
±10
200
200
20
15
0.8
0.45
V
CC
+0.5
Unit
µA
µA
µA
mA
µA
mA
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
µA
µA
mA
µA
µA
V
I
OH
= -2.5mA, V
CC
= 4.5V
A
9
= V
ID
A
9
= V
ID
RP
= GND±0.2V
Erase Suspended
CE
= V
IH
Erase Suspended V
PP
=V
PPH
RP
= V
HH
V
CC
= V
CCMIN
I
OH
= -1.5mA
I
OL
= 5.8mA, V
CC
= 4.5V
Test Conditions
V
IN
= V
CC
or V
SS
V
CC
= 5.5V
V
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V
CE
= V
CC
±0.2V
=
RP
V
CC
= 5.5V
CE
=
RP
= V
IH
, V
CC
= 5.5V
RP
= GND±0.2V
V
CC
= 5.5V, CE = GND,
I
OUT
= 0mA, f = 10 MHz
V
CC
= 5.5V,
Programming in Progress
V
CC
= 5.5V,
Erase in Progress
V
PP
<
V
CC
V
PP
>
V
CC
V
PP
= V
PPH
V
PP
= V
PPH
,
Programming in Progress
V
PP
= V
PPH
,
Erase in Progress
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25072-00 2/98 F-1
4
CAT28F002
SUPPLY CHARACTERISTICS
Limits
Symbol
V
LKO
V
CC
V
PPL
V
PPH
V
HH
V
PPLK
Parameter
V
CC
Erase/Write Lock Voltage
V
CC
Supply Voltage
V
PP
During Read Operations
V
PP
During Erase/Program
RP, OE
Unlock Voltage
V
PP
Lock-Out Voltage
Min
2.0
4.5
0
11.4
10.8
0
5.5
6.5
12.6
13.2
6.5
Max.
Unit
V
V
V
V
V
V
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V
±10%,
unless otherwise specified
JEDEC Standard
Symbol
t
AVAV
t
ELQV
t
AVQV
t
GLQV
-
t
GLQX
t
ELQX
t
GHQZ
t
EHQZ
t
PHQV
Symbol
t
RC
t
CE
t
ACC
t
OE
t
OH
t
LZ(1)(6)
t
DF(1)(2)
t
HZ(1)(2)
t
PWH
Parameter
Read Cycle Time
CE
Access Time
Address Access Time
OE
Access Time
Output Hold from Address
OE/CE
Change
0
0
0
30
30
300
28F002-90
Min. Max.
90
90
90
40
0
0
0
30
30
300
28F002-12 28F002-15
Min. Max. Min. Max. Unit
120
120
120
40
0
0
0
30
30
300
150
150
150
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
OLZ(1)(6)
OE
to Output in Low-Z
CE
to Output in Low-Z
OE
High to Output High-Z
CE
High to Output High-Z
RP
High to Output Delay
Figure 1. A.C. Testing Input/Output Waveform
(3)(4)(5)
2.4 V
INPUT PULSE LEVELS
0.45 V
0.8 V
5108 FHD F03
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
5108 FHD F04
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
5
Doc. No. 25072-00 2/98 F-1
FPGA/CPLD
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