CAT310
10 Channel Automotive LED Display Driver
FEATURES
Automotive “load dump” protection (40V)
10 independent LED channels
Up to 50mA output per channel
Overvoltage detection at 19V
Serial interface for channel programming
Daisy chain output for multi-driver cascading
LED blanking control
Operating temperature from -40ºC to +125ºC
20-pin SOIC package
PRODUCT DESCRIPTION
The CAT310 is a 10-channel LED driver for
automotive and other lighting applications. All
LED output channels are driven from a low
on-resistance open-drain High Voltage CMOS
Nch-FETs and are fully compliant with “Load
Dump” transients of up to 40 volts. The LED
bias current of each channel can be set
independently using an external series ballast
resistor, making the device ideal for multi-
color instrumentation displays.
A high-speed serial interface (suitable with
both 3.3 volt and 5 volt systems) feeding a
10 bit shift register is used to program the
desired state (on/off) of each channel. The
device offers a blanking control pin (BLANK)
which can be used to disable all channels on
demand. A serial output data pin (SOUT) is
provided to daisy-chain devices in large
cluster LED applications
During initial power up all channels are reset
and cleared via an under-voltage lock out
(UVLO) detector and for added protection all
channels are disabled in the event of a
battery over-voltage condition (19 volts or
more).
APPLICATIONS
Automotive lighting
White and other color high brightness LEDs
Multi-color high-brightness LED cluster displays
General LED lighting
ORDERING INFORMATION
Part
Number
CAT310W
Package
SOIC-20
Lead free
Quantity
per Reel
1000
Package
Marking
CAT310W
For Ordering Information details, see page 10.
TYPICAL APPLICATION CIRCUIT
PIN DIAGRAM
SOIC 20-pin package
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. 25087, Rev. 2
CAT310
ABSOLUTE MAXIMUM RATINGS
Parameter
VCC voltage
Input voltage range (SIN, SCLK, BLANK, XLAT)
SOUT voltage range
Peak OUT0 to OUT9 voltage
VBATT input voltage
DC output current on OUT0 to OUT9
Storage Temperature Range
Operating Junction Temperature Range
Lead Soldering Temperature (10sec.)
ESD Rating: Low Voltage Pins
Human Body Model
Machine Model
ESD Rating: VBATT, OUT[0:9] pins
Human Body Model
Machine Model
Rating
7
-0.3V to VCC+0.3V
-0.3V to VCC+0.3V
40
40
70
-55 to +160
-40 to +150
300
3000
300
1000
100
Unit
V
V
V
V
V
mA
°C
°C
°C
V
V
RECOMMENDED OPERATING CONDITIONS
Parameter
VCC
Voltage applied to OUT0 to OUT9
Output current on OUT0 to OUT9
Ambient Temperature Range
Range
3.0 to 5.5
9 to 17
0 to 50
-40 to +125
Unit
V
V
mA
°C
ELECTRICAL OPERATING CHARACTERISTICS
DC Characteristics
VCC = 5.0V, -40ºC
≤
T
A
≤
125 ºC, over recommended operating conditions unless
specified otherwise.
Symbol Name
I
STBY
Standby Quiescent Current
V
OVP
V
UVLO
R
SW
I
O(n)LKG
I
XLAT
I
BLANK
V
IH
V
IL
I
IL
V
OH
V
OL
Conditions
Static input signal. All
outputs turned off.
Min
Typ
1
19
1.7
I
O(n)
= 30mA
V
(OUT(n))
= 15V
XLAT = V
CC
XLAT = 0.3V
BLANK = 0V
BLANK = V
CC
- 0.3V
V
I
= V
CC
or GND
I
OH
= -1mA
I
OL
= 1mA
2
Max
10
21
2.5
12
10
30
6
30
6
0.7V
CC
5
0.3
Units
µA
V
V
Ω
µA
µA
µA
V
µA
V
VBATT Over Voltage
Protection Trigger threshold
VCC Under Voltage Lockout
Trigger threshold
Switch on resistance for
OUT0 to OUT9
OUT0 to OUT9 Output Switch
Leakage
XLAT Internal Pull-down
current
BLANK Internal Pull-up
current
Logic high input voltage
Logic low input voltage
Logic Input leakage current
(SCLK, SIN)
SOUT logic high output voltage
SOUT logic low output voltage
17
2
5
0.1
4
1
4
1
0.3 V
CC
-5
V
CC
-0.3V
10
3
10
3
0
Doc. No. 25087, Rev. 2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT310
ELECTRICAL OPERATING CHARACTERISTICS
Switching Characteristics
VCC = 5.0V, -40ºC
≤
T
A
≤
125 ºC, over recommended operating conditions
unless specified otherwise.
Symbol
SCLK
f
SCLK
t
wh/wl
SIN
t
su
t
h
XLAT
t
w
t
h
t
r
t
f
t
pd
t
pd
t
pd
Name
SCLK Clock Frequency
SCLK Pulse width
Setup time SIN to SCLK
Hold time SIN to SCLK
XLAT Pulse width
Hold time
SCLK to XLAT
SOUT rise time (10% to 90%)
SOUT fall time (90% to 10%)
Propagation delay time
Propagation delay time
Propagation delay time
SIN to SCLK
Conditions
Min
Typ
Max
10
High or Low
30
10
10
20
20
C
L
= 15pF
C
L
= 15pF
Blank
↑
to OUT(n)
Blank
↓
to OUT(n)
SCLK to SOUT
20
15
25
25
25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All logic inputs contain Schmitt trigger inputs.
BLOCK DIAGRAM
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. 25087, Rev. 2
CAT310
PIN DESCRIPTIONS
VCC
is the supply input for the internal logic
and is compatible with both 3.3V and 5V
systems. The logic is held in a reset state
until VCC exceeds 2.5V. It is recommended
that a small bypass ceramic capacitor (1uF)
be placed between VCC and GND pins on
the device.
BLANK
is the CMOS logic input (active high)
used to temporarily disable all outputs. An
internal pull-up current of 10 microampere is
present on this pin. The BLANK pin must be
driven to a logic low in order for channel outputs
to resume normal operation. An external pull-
down resistance of 10kΩ or less is adequate for
logic low.
SIN
is the CMOS logic pin for delivering the
serial input data stream into the internal 10-
bit shift register. The most recent or last data
value in the serial stream is used to
configure the state of output channel “zero”
(OUT0). During the initial power up
sequence all contents of the shift register are
reset and cleared to zero.
SOUT
is the CMOS logic output used for daisy
chain applications. The serial output data stream
is fed from the last stage of the internal 10-bit
shift register. On each rising edge of the clock,
the SOUT value will be updated. The data value
present on this pin is identical to the data value
being used for configuring the state of output
channel nine (OUT9). At initial power up, the
SOUT data stream will contain all zeroes until the
shift register has been fully loaded.
SCLK
is the CMOS logic pin used to clock
the internal shift register. On each rising
edge of clock, the serial data will advance
through one stage of the shift register.
VBATT
input monitors the battery voltage. If an
over-voltage, above 19V typical, is detected, all
outputs are disabled. Upon conclusion of the
over-voltage condition, all outputs resume normal
operation. The current drawn by the VBATT pin is
less than 1 microampere during normal operation.
XLAT
is the CMOS logic input used to
transfer data from the 10-bit shift register into
the output channel latches. An internal pull-
down current of 10 microampere is present on
this pin. When XLAT is low, the state of each
output channel remains unchanged. When
XLAT is driven high, the contents of the shift
register appear at their respective output
channels. An external pull-up resistance of
10kΩ or less is adequate for logic high.
OUT0-OUT9
are the ten LED outputs connected
internally to the switch N-channel FETs. They
sink currents up to 50mA per channel and can
withstand transients up to 40V compatible with
automotive “load dump”. The output on-
resistance is 5Ω, and the off-resistance is 5MΩ.
PGND, GND
pins should be connected to
the ground on the PCB.
PIN TABLE
Pin Number
1
2
3
4
5
6-10
11-15
16
17
18
19
20
Doc. No. 25087, Rev. 2
Pin Name
SCLK
XLAT
SIN
SOUT
GND
OUT4 - OUT0
OUT9 - OUT5
PGND
VBATT
VCC
BLANK
N.C.
Description/Function
Clock input for the data shift register.
Control input for the data latch.
Serial data input.
Serial data output.
Ground.
Open drain outputs.
Open drain outputs.
Ground for LED driver outputs.
Battery sense input.
Power supply voltage for the logic
Blank input. When BLANK is high, all the output drivers are turned off.
No connect.
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT310
TYPICAL CHARACTERISTICS
VCC = 5V, VBATT = 14V, T
AMB
= 25ºC, unless otherwise specified.
VBATT Overvoltage Detection
Amplitude between 16V and 26V
BLANK and Output waveform
18V
XLAT pull-down Current vs. Input Voltage
14
12
XLAT CURRENT [uA]
10
8
6
4
2
0
0
1
2
3
4
XLAT VOLTAGE [V]
5
125ºC
85ºC
-40ºC
25ºC
BLANK pull-up Current vs. Input Voltage
14
BLANK CURRENT [uA]
12
10
8
6
4
2
0
0
1
2
3
4
BLANK VOLTAGE [V]
5
VCC = 5V
85ºC
125ºC
25ºC
-40ºC
VBATT Load Dump
40V
Switch On-resistance vs. VCC
12
SWITCH ON RESISTANCE [Ω]
10
125ºC
8
6
4
2
0
2
3
4
5
VCC VOLTAGE [V]
6
-40ºC
25ºC
85ºC
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. 25087, Rev. 2
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