CAT5251
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
Four linear-taper digitally programmable
potentiometers
254 resistor taps per potentiometer
End to end resistance 50kΩ or 100kΩ
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
SOIC 24-lead and TSSOP 24-lead
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of resistive elements connected between
two externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC 24-Lead (W)
TSSOP 24-Lead (Y)
SO
A0
R
W3
R
H3
R
L3
NC
V
CC
R
LO
R
HO
R
WO
¯¯¯
CS
¯¯¯
WP
1
2
3
4
5
24
23
22
21
20
¯¯¯¯¯
HOLD
SCK
R
L2
R
H2
R
W2
NC
GND
R
W1
R
H1
R
L1
A1
SI
WP
A0
A1
HOLD
CS
SCK
SI
SO
FUNCTIONAL DIAGRAM
R
H0
R
H1
R
H2
R
H3
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
R
W1
R
W2
6
CAT
19
7
5251
18
8
9
10
11
12
17
16
15
14
13
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
R
L2
R
L3
R
W3
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2017 Rev. G
CAT5251
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1:
Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four devices
can be addressed on a single bus. A match in the
slave address must be made with the address input
in order to initiate communication with the CAT5251.
R
H
, R
L
:
Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
:
Wiper
The four R
W
pins are equivalent to the wiper terminal
of a mechanical potentiometer.
¯¯¯:
Chip Select
CS
¯¯¯ is the Chip select pin. ¯¯¯ low enables the
CS
CS
¯¯¯ high disables the CAT5251. ¯¯¯
CAT5251 and CS
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on ¯¯¯ is required prior to any
CS
sequence being initiated. A low to high transition on
¯¯¯ after a valid write sequence is what initiates an
CS
internal write cycle.
¯¯¯:
Write Protect
WP
¯¯¯ is the Write Protect pin. The Write Protect pin
WP
will allow normal read/write operations when held
high. When ¯¯¯ is tied low, all non-volatile write
WP
operations to the Data registers are inhibited
(change of wiper control register is allowed). ¯¯¯
WP
going low while ¯¯¯ is still low will interrupt a write to
CS
the registers. If the internal write cycle has already
been initiated, ¯¯¯ going low will have no effect on
WP
any write operation.
¯¯¯¯¯
HOLD:
Hold
The ¯¯¯¯¯ pin is used to pause transmission to the
HOLD
CAT5251 while in the middle of a serial sequence
without having to re-transmit entire sequence at a
¯¯¯¯¯
later time. To pause, HOLD must be brought low
while SCK is low. The SO pin is in a high impedance
state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
¯¯¯¯¯
communication, HOLD is brought high, while SCK is
¯¯¯¯¯
low. (HOLD should be held high any time this
¯¯¯¯¯
function is not being used.) HOLD may be tied high
directly to V
CC
or tied to V
CC
through a resistor.
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
SO
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
¯¯¯
CS
¯¯¯
WP
SI
A1
R
L1
R
H1
R
W1
GND
NC
R
W2
R
H2
R
L2
SCK
¯¯¯¯¯
HOLD
Function
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal for
Potentiometer 3
Low Reference Terminal for
Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for Potentiometer 2
High Reference Terminal for
Potentiometer 2
Low Reference Terminal for
Potentiometer 2
Bus Serial Clock
Hold
Doc. No. MD-2017 Rev. G
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5251
SERIAL BUS PROTOCOL
The CAT5251 supports the SPI bus data
transmission protocol. The synchronous Serial
Peripheral Interface (SPI) helps the CAT5251 to
interface directly with many of today's popular
microcontrollers. The CAT5251 contains an 8-bit
instruction register. The instruction set and the
operation codes are detailed in Table 3, Instruction
Set on page 8.
After the device is selected with ¯¯¯ going low the
CS
first byte will be received. The part is accessed via
the SI pin, with data being clocked in on the rising
edge of SCK. The first byte contains one of the six
op-codes that define the operation to be performed.
DEVICE OPERATION
The CAT5251 is four resistor arrays integrated with an
SPI serial interface logic, four 8-bit wiper control
registers and sixteen 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series
resistors are connected to the output wiper terminals
(R
W
) by a CMOS transistor switch. Only one tap point
for each potentiometer is connected to its wiper terminal
at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data
registers via the SPI bus. Additional instructions allow
data to be transferred between the wiper control
registers and each respective potentiometer's non-
volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
ABSOLUTE MAXIMUM RATINGS
(1)
Parameter
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS(2)(3)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
Recommended Operating Conditions
V
CC
= +2.5V to +6V
Parameter
Operating Ambient Temperature (Industrial)
Ratings
-40 to +85
Units
°C
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+2.0
-2.0 to +7.0
1.0
300
±6
Units
°C
°C
V
V
W
°C
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2)
(3)
The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20ns.
Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
3
Doc. No. MD-2017 Rev. G
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5251
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
R
POT
R
POT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Test Conditions
Min
Typ
100
50
±20
1
50
±3
300
150
V
CC
Max
Units
kΩ
kΩ
%
%
mW
mA
Ω
Ω
V
nV/√Hz
%
LSB
(4)
LSB
(4)
ppm/°C
ppm/°C
pF
MHz
25°C, each pot
I
W
= ±3mA @ V
CC
= 3V
I
W
= ±3mA @ V
CC
= 5V
V
SS
= 0V
(1)
R
W(n)(actual)
- R
(n)(expected)(5)
R
W(n+1)
- [R
W(n)+LSB
]
(5)
(1)
(1)
(1)
R
POT
= 50kΩ
(1)
200
100
GND
0.4
I
W
R
W
V
TERM
V
N
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(2)
Relative Linearity
(3)
TC
RPOT
Temperature Coefficient of R
POT
TC
RATIO
Ratiometric Temp. Coefficient
C
H
/C
L
/C
W
Potentiometer Capacitances
fc
Frequency Response
±1
±0.5
±300
20
10/10/25
0.4
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OH1
Parameter
Power Supply Current
Power Supply Current
Non-volatile Write
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3V)
Output High Voltage (V
CC
= 6V)
I
OL
= 3mA
I
OH
= -1.6mA
V
CC
- 0.8
Test Conditions
f
SCK
= 2.5MHz, SO Open
V
CC
= 6V Inputs = GND
f
SCK
= 2.5MHz, SO = Open
V
CC
= 6V Inputs = GND
V
IN
= GND or V
CC
; SO Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Typ
Max
1
5
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
(3)
(4)
(5)
Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
n = 0, 1, 2, ..., 255.
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Doc. No. MD-2017 Rev. G
CAT5251
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
= 25ºC, f = 1.0MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Parameter
Output Capacitance (SO)
¯¯¯
Input Capacitance (CS , SCK, SI, ¯¯¯, HOLD, A0, A1)
WP ¯¯¯¯¯
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Parameter
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
¯¯¯¯¯
HOLD to Output Low Z
Input Rise Time
Input Fall Time
¯¯¯¯¯
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
¯¯¯¯¯
HOLD to Output High Z
¯¯¯ High Time
CS
¯¯¯ Setup Time
CS
¯¯¯ Hold Time
CS
250
250
250
0
250
100
C
L
= 50pF
100
100
200
Test Conditions
Min
50
50
125
125
DC
3
50
2
2
Typ
Max
Units
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
POWER UP TIMING
(1)(2)
Over recommended operating conditions unless otherwise stated.
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
WIPER TIMING
Symbol
t
WRPO
t
WRL
Parameter
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Min
5
5
Max
10
10
Units
µs
µs
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
5
Doc. No. MD-2017 Rev. G
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
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