CAT5411
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
Two linear-taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
24-lead SOIC and 24-lead TSSOP
Industrial temperature ranges
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
DESCRIPTION
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the two potentiometers is
automatically loaded into its respective wiper control
register.
PIN CONFIGURATION
SOIC (W)
(top view)
V
CC
R
L0
R
H0
R
W0
¯¯¯
CS
¯¯¯
WP
SI
A
1
R
L1
R
H1
R
W1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
NC
NC
NC
NC
A
0
SO
¯¯¯¯¯
HOLD
SCK
NC
NC
NC
NC
SI
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
¯¯¯¯¯
HOLD
FUNCTIONAL DIAGRAM
TSSOP (Y)
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
¯¯¯
WP
¯¯¯
CS
R
W0
R
H0
R
L0
V
CC
NC
NC
NC
NC
A
0
SO
R
L0
R
L1
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
W1
CS
SCK
SI
SO
WIPER
CONTROL
REGISTERS
R
H0
R
H1
SPI BUS
INTERFACE
R
W0
CAT
19
5411
18
17
16
15
14
13
CAT
19
5411
18
17
16
15
14
13
For Ordering Information details, see page 15.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2114 Rev. I
CAT5411
PIN DESCRIPTIONS
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5411. During a read cycle, data is
shifted out on the falling edge of the serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
A0, A1:
Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed
on a single bus. A match in the slave address must be
made with the address input in order to initiate
communication with the CAT5411.
R
H
, R
L
:
Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
:
Wiper
The four R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
¯¯¯:
Chip Select
CS
CAT5251 and ¯¯¯ high disables the CAT5411. ¯¯¯ high
CS
CS
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO
current in the Standby mode. A high to low transition on
¯¯¯ is required prior to any sequence being initiated. A low
CS
to high transition on ¯¯¯ after a valid write sequence is
CS
what initiates an internal write cycle.
¯¯¯:
Write Protect
WP
¯¯¯ is the Write Protect pin. The Write Protect pin will
WP
allow normal read/write operations when held high.
When ¯¯¯ is tied low, all non-volatile write operations to
WP
the Data registers are inhibited (change of wiper control
register is allowed). ¯¯¯ going low while ¯¯¯ is still low will
WP
CS
interrupt a write to the registers. If the internal write cycle
has already been initiated, ¯¯¯ going low will have no
WP
effect on any write operation.
Pin
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
TSSOP
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
V
CC
R
L0
R
H0
R
W0
¯¯¯
CS
¯¯¯
WP
SI
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
¯¯¯¯¯
HOLD
SO
A
0
NC
NC
NC
NC
Function
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for
Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
¯¯¯¯¯
HOLD:
Hold
¯¯¯¯¯
The HOLD pin is used to pause transmission to the
CAT5411 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
¯¯¯¯¯
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
¯¯¯¯¯
resume communication, HOLD is brought high, while SCK
¯¯¯¯¯
is low. (HOLD should be held high any time this function is
¯¯¯¯¯
not being used.) HOLD may be tied high directly to V
CC
or
tied to V
CC
through a resistor.
Doc. No. MD-2114 Rev. I
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
DEVICE OPERATION
The CAT5411 is two resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and eight 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
).
R
H
and R
L
are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (R
W
) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the non-
volatile memory data registers via the SPI bus.
Additional instructions allow data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with
many
of
today's
popular
microcontrollers.
The CAT5041 contains an 8-bit instruction register.
The instruction set and the operation codes are
detailed in the instruction set table 3.
After the device is selected with ¯¯¯ going low the first
CS
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
N
END (1)
TDR
(1)
V
ZAP(1)
I
LTH(1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2114 Rev. I
CAT5411
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Range
Voltage to any Pins with
Respect to V
SS (2) (3)
V
CC
with Respect to GND
Package Power Dissipa-
tion Capability (T
A
= 25°C)
Lead Soldering
Temperature (10s)
Wiper Current
Ratings
-55 to +125
-65 to +150
-2.0 to V
CC
+2.0
-2.0 to +7.0
1.0
300
±12
Units
ºC
ºC
V
V
W
ºC
mA
(3)
RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to 6.0
-40 to +85
Units
V
ºC
Notes:
(1) Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions outside of those listed in the
operational sections of this specification is not implied.
Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
(2)
The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V
CC
+0.5V, which may
overshoot to V
CC
+2.0V for periods of less than 20 ns.
Latch-up protection is provided for stresses up to 100 mA on
address and data pins from –1V to V
CC
+1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(2)
Relative Linearity
(3)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
W(n)(actual)
-R
(n)(expected)(5)
R
W(n+1)
-[R
W(n)+LSB
]
(5)
(1)
(1)
(1)
Test Conditions
Min
Typ
100
50
10
2.5
Max
Units
kΩ
kΩ
kΩ
kΩ
+20
1
25°C, each pot
I
W
= +3mA @ V
CC
= 3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
(1)
%
%
mW
mA
Ω
Ω
V
nV/√Hz
%
50
+6
300
80
GND
1.6
+1
+0.2
+300
20
10/10/25
150
V
CC
LSB
(4)
LSB
(4)
ppm/°C
ppm/°C
pF
MHz
R
POT
= 50kΩ
(1)
0.4
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Doc. No. MD-2114 Rev. I
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
Test Conditions
f
SCK
= 2MHz, SO
Open Inputs = GND
V
IN
= GND or V
CC
; SO Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
µA
µA
µA
V
V
V
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
= 25˚C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (¯¯¯, SCK, SI, ¯¯¯, HOLD)
CS
WP ¯¯¯¯¯
Min
Typ
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
POWER UP TIMING
(1)
Over recommended operating conditions unless otherwise stated.
Symbol
t
PUR(2)
t
PUW(2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
5
Doc. No. MD-2114 Rev. I
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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