74HC590
8-bit binary counter with output register; 3-state
Rev. 01 — 30 March 2005
Product data sheet
1. General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features a master
reset counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state always is one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks
are connected together, the counter state always is one count ahead of the register.
2. Features
s
s
s
s
s
Counter and register have independent clock inputs
Counter has master reset
Complies with JEDEC standard no. 7A
Multiple package options
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
x
CDM EIA/JESD22-C101C exceeds 2000 V
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Symbol
t
PHL
, t
PLH
Parameter
Conditions
Min
-
-
-
-
Typ
19
17
18
13
Max Unit
-
-
-
-
ns
ns
ns
ns
propagation delay CPC to C
L
= 50 pF; V
CC
= 4.5 V
RCO
propagation delay CPR to C
L
= 50 pF; V
CC
= 4.5 V
Qn
t
PLH
t
PZH
, t
PZL
propagation delay MRC to C
L
= 50 pF; V
CC
= 4.5 V
RCO
3-state output enable time C
L
= 50 pF; V
CC
= 4.5 V
OE to Qn
Philips Semiconductors
74HC590
8-bit binary counter with output register; 3-state
Table 1:
Quick reference data
…continued
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Symbol
t
PHZ
, t
PLZ
C
I
C
PD
Parameter
Conditions
Min
-
-
[1] [2]
Typ
13
3.5
44
Max Unit
-
-
-
ns
pF
pF
3-state output disable time C
L
= 50 pF; V
CC
= 4.5 V
OE to Qn
input capacitance
power dissipation
capacitance
-
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
The condition is V
I
= GND to V
CC
.
[2]
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74HC590D
74HC590PW
74HC590BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
TSSOP16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual-in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals; body
2.5
×
3.5
×
0.85 mm
9397 750 14691
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 30 March 2005
2 of 25
Philips Semiconductors
74HC590
8-bit binary counter with output register; 3-state
5. Functional diagram
12 CE
11 CPC
10 MRC
8-BIT BINARY COUNTER
13 CPR
8-BIT STORAGE REGISTER
RCO 9
Q0 15
Q1 1
Q2 2
Q3 3
14 OE
3-STATE OUTPUTS
Q4 4
Q5 5
Q6 6
Q7 7
001aac542
Fig 1. Functional diagram
OE
CPR
14
13
12
11
10
EN3
C2
G1
11
CPC
13
CPR
RCO
Q0
Q1
Q2
9
15
1
CE
CPC
MRC
CTR8
(CT=255)Z4
9
RCO
1+
CT=0
1D
2D
3
15
1
2
3
4
5
6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
3
4
5
6
7
12
CE
Q3
Q4
Q5
Q6
Q7
MRC
10
OE
2D
3
7
14
001aac544
001aac545
Fig 2. Logic symbol
Fig 3. IEC logic symbol
9397 750 14691
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 30 March 2005
3 of 25
Philips Semiconductors
74HC590
8-bit binary counter with output register; 3-state
OE
14
CPR
13
CE
CPC
12
11
9
RCO
T
MRC
10
R
1R
C1
1S
15
Q0
T
R
1R
C1
1S
1
Q1
T
R
1R
C1
1S
2
Q2
T
R
1R
C1
1S
3
Q3
T
R
1R
C1
1S
4
Q4
T
R
1R
C1
1S
5
Q5
T
R
1R
C1
1S
6
Q6
T
R
1R
C1
1S
7
Q7
001aac543
Fig 4. Logic diagram
9397 750 14691
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 30 March 2005
4 of 25
Philips Semiconductors
74HC590
8-bit binary counter with output register; 3-state
6. Pinning information
6.1 Pinning
terminal 1
index area
Q2
Q3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aac564
2
3
4
5
6
7
8
GND
RCO
9
16 V
CC
15 Q0
14 OE
13 CPR
12 CE
11 CPC
10 MRC
001aac547
16 V
CC
15 Q0
14 OE
13 CPR
12 CE
11 CPC
10 MRC
9
RCO
Q4
Q5
Q6
Q7
74HC590
GND
(1)
74HC590
Transparent top view
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO16 and
TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 3:
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
RCO
MRC
CPC
CE
CPR
OE
Q0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
ripple carry output (active LOW)
master reset counter input (active LOW)
counter clock input (active HIGH)
count enable input (active LOW)
register clock input (active HIGH)
output enable input (active LOW)
parallel data output 0
supply voltage
9397 750 14691
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 30 March 2005
1
Q1
5 of 25
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