74LVC3G04
Triple inverter
Rev. 11 — 2 April 2013
Product data sheet
1. General description
The 74LVC3G04 provides three inverting buffers.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC3G04
Triple inverter
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC3G04DP
74LVC3G04DC
74LVC3G04GT
74LVC3G04GF
74LVC3G04GD
74LVC3G04GM
74LVC3G04GN
74LVC3G04GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-2
SOT1116
SOT1203
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
V04
V04
V04
V4
V04
V04
V4
V4
Type number
74LVC3G04DP
74LVC3G04DC
74LVC3G04GT
74LVC3G04GF
74LVC3G04GD
74LVC3G04GM
74LVC3G04GN
74LVC3G04GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC3G04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 2 April 2013
2 of 21
NXP Semiconductors
74LVC3G04
Triple inverter
5. Functional diagram
1
1A
1Y
1
2A
2Y
1
A
001aah793
001aah794
3A
3Y
Y
mna110
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one driver)
6. Pinning information
6.1 Pinning
74LVC3G04
1A
1
8
V
CC
3Y
2
7
1Y
74LVC3G04
1A
3Y
2A
GND
1
2
3
4
001aad954
8
7
6
5
V
CC
1Y
3A
2Y
2A
3
6
3A
GND
4
5
2Y
001aad955
Transparent top view
Fig 4.
Pin configuration SOT505-2 and SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC3G04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 2 April 2013
3 of 21
NXP Semiconductors
74LVC3G04
Triple inverter
74LVC3G04
terminal 1
index area
1Y
1
V
CC
8
74LVC3G04
1A
3Y
2A
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
3A
1Y
3A
2Y
2Y
2
6
3Y
3
4
5
2A
GND
001aad956
001aai254
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
Fig 7.
Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1A, 2A, 3A
GND
1Y, 2Y, 3Y
V
CC
1, 3, 6
4
7, 5, 2
8
SOT902-2
7, 5, 2
4
1, 3, 6
8
data input
ground (0 V)
data output
supply voltage
Description
7. Functional description
Table 4.
Input nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output nY
H
L
74LVC3G04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 2 April 2013
4 of 21
NXP Semiconductors
74LVC3G04
Triple inverter
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 package: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
C
the value of P
tot
derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC3G04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 2 April 2013
5 of 21
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