INTEGRATED CIRCUITS
74LVT240
ABT octal inverting buffer (3-State)
Product specification
Supersedes data of 1994 May 16
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal inverting buffer (3-State)
74LVT240
FEATURES
•
Octal bus interface
•
3-State buffers
•
Output capability: +64mA/-32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5V bus
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model.
resistors to hold unused inputs
Power-up 3-State
DESCRIPTION
The LVT240 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device is an octal inverting buffer that is ideal for driving bus
lines. The device features two Output Enables (1OE, 2OE), each
controlling four of the 3-State outputs.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nAx to nYx
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3.0V
Outputs disabled; V
O
= 0V or 3.0V
Outputs disabled; V
CC
= 3.6V
TYPICAL
2.5
2.6
4
8
0.12
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT240 D
74LVT240 DB
74LVT240 PW
NORTH AMERICA
74LVT240 D
74LVT240 DB
74LVT240PW DH
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
2, 4, 6, 8
SYMBOL
1A0 – 1A3
2A0 – 2A3
1Y0 – 1Y3
2Y0 – 2Y3
1OE, 2OE
GND
V
CC
NAME AND FUNCTION
Data inputs
Data inputs
Data outputs
Data outputs
Output enables
Ground (0V)
Positive supply voltage
1OE
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
2OE
1Y0
2A3
1Y1
2A2
1Y2
2A1
1Y3
2A0
11, 13, 15, 17
18, 16, 14, 12
9, 7, 5, 3
1, 19
10
20
GND 10
SV00006
1998 Feb 19
2
853-1744 18991
Philips Semiconductors
Product specification
3.3V Octal inverting buffer (3-State)
74LVT240
LOGIC SYMBOL
2 1A0
4 1A1
6
8
1A2
1A3
1Y0
1Y1
1Y2
1Y3
18
16
14
12
LOGIC SYMBOL (IEEE/IEC)
1
EN
2
4
6
8
18
16
14
12
1 1OE
11
13
2A0
2A1
2Y0
9
2Y1
2Y2
2Y3
7
5
3
19
EN
15 2A2
17 2A3
19
2OE
11
13
15
17
9
7
5
3
SV00007
SV00008
FUNCTION TABLE
INPUTS
nOE
L
L
H
L
X
Z
=
=
=
=
nAx
L
H
OUTPUTS
nYx
H
L
Z
H
X
High voltage level
Low voltage level
Don’t care
High impedance “Off” state
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
V
I
V
OUT
I
O
OUT
I
IK
I
OK
T
stg
PARAMETER
DC supply voltage
DC input voltage
3
DC output voltage
3
DC output current
Output in High state
DC input diode current
DC output diode current
Storage temperature range
V
I
< 0
V
O
< 0
–64
–50
–50
–65 to 150
mA
mA
°C
Output in Off or High state
Output in Low state
CONDITIONS
RATING
–0.5 to +4.6
–0.5 to +7.0
–0.5 to +7.0
128
mA
UNIT
V
V
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
1998 Feb 19
3
Philips Semiconductors
Product specification
3.3V Octal inverting buffer (3-State)
74LVT240
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
–40
PARAMETER
LIMITS
MIN
2.7
0
2.0
0.8
–32
32
64
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
V
IK
V
OH
PARAMETER
Input clamp voltage
High-level output voltage
TEST CONDITIONS
V
CC
= 2.7V; I
I
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100µA
V
CC
= 2.7V; I
OH
= –8mA
V
CC
= 3V; I
OH
= –32mA
V
CC
= 2.7V; I
OL
= 100µA
V
CC
= 2.7V; I
OL
= 24mA
V
OL
Low-level output voltage
V
CC
= 3V; I
OL
= 16mA
V
CC
= 3V; I
OL
= 32mA
V
CC
= 3V; I
OL
= 64mA
V
CC
= 0 or 3.6V; V
I
= 5.5V
I
I
Input leakage current
In ut
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0
I
OFF
I
HOLD
Output off current
Bus Hold current A
in uts
inputs
NO TAG
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State
output current
3
3-State output High current
3-State output Low current
Quiescent supply current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
CC
= 0V to 3.6V; V
CC
= 3.6V
I
EX
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current
per input pin
2
V
O
= 5.5V; V
CC
= 3.0V
V
CC
=
≤
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6V; V
O
= 3.0V
V
CC
= 3.6V; V
O
= 0.5V
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
NO TAG
V
CC
= 3.0 to 3.6V; One input at V
CC
-0.6V;
Other inputs at V
CC
or GND
75
–75
±500
60
±1
1
–1
0.12
3
0.12
0.1
125
±100
5
–5
0.19
12
0.19
0.2
mA
mA
µA
µA
µA
µA
Control pins
Data pins
4
ins
V
CC
-0.2
2.4
2
T
amb
= -40°C to +85°C
MIN
TYP
1
0.9
V
CC
-0.1
2.5
2.2
0.1
0.3
0.25
0.3
0.4
1
±0.1
0.1
–1
1
150
–150
µA
0.2
0.5
0.4
0.5
0.55
10
±1
1
-5
±100
µA
µA
V
MAX
–1.2
V
V
V
V
UNIT
NOTES:
1. All typical values are at T
amb
= 25°C.
2. This is the increase in supply current for each input at V
CC
–0.6V.
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
10% a
transition time of 100µsec is permitted. This parameter is valid for T
amb
= 25°C, only.
4. Unused pins at V
CC
or GND
5. I
CCZ
is measured with outputs pulled to V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal inverting buffer (3-State)
74LVT240
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF; R
L
= 500Ω;T
amb
= –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= –40°C to +85°C
V
CC
= +3.3V
±0.3V
MIN
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
nAx to nYx
Output enable time
to High and Low level
Output disable time
from High and Low level
1
2
2
1
1
1
1
2
1.6
TYP
1
2.5
2.5
3.7
3.1
3.4
3.2
MAX
4.3
4.3
5.2
5.2
5.6
5.1
V
CC
= 2.7V
MAX
5.2
5.0
6.3
6.7
6.3
5.6
ns
ns
ns
UNIT
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 2.7V
V
IN
V
IN
nOE INPUT
nAx INPUT
V
M
V
M
V
MI
V
MI
0V
t
PZL
t
PHL
t
PLH
nYx OUTPUT
nYx OUTPUT
V
M
V
M
V
MO
t
PLZ
3.0V
V
OL
+ 0.3V
t
PZH
t
PHZ
V
OL
V
OH
nYx OUTPUT
V
MO
V
OH
– 0.3V
SA00037
Waveform 1. Input (nAx) to Output (nYx) Propagation Delays
0V
SV00104
Waveform 2. 3-State Output Enable and Disable Times
1998 Feb 19
5
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