INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7132
Quad precision adjustable
Schmitt-trigger / comparator with
output latches; 3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger /
comparator with output latches; 3-state
FEATURES
•
Precision inputs
•
2 operation modes: PAST and
comparator
•
In PAST mode: Inverting outputs in
view of the precision oscillator
application
•
In comparator mode: Non-inverting
outputs to simplify the design of an
external hysteresis network
•
3-state outputs for bus oriented
applications
•
Output capability: Bus driver
•
I
CC
category: MSI
APPLICATIONS
•
Precision oscillators
•
Signal reconditioning
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
SYMBOL
V
rH
V
rL
δV
t
C
PD
PARAMETER
High trip level
reference level
Low trip level
DC inaccuracy
power dissipation
capacitance per function
CONDITIONS
PAST mode; V
CC
= 3 to 6 V
Comparator mode; V
CC
= 3 to 6 V
PAST mode; V
CC
= 3 to 6 V
V
CC
= 3 to 6 V
V
CC
= 5 V
PAST mode
Comparator mode
P
d
t
rmin
/t
fmin
t
PHL
/t
PLH
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
C
L
×
V
CC2
×
f
o
where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacity in pF;
V
CC
= supply voltage in V.
September 1993
2
Total DC power dissipation Comparator mode; V
CC
= 4.5 V;
V
rL
= V
INn
= 0 V; V
rH
= 2.25 V
Minimum rise and fall time
for optimum operation
propagation delay
V
inn
to Q
PAST mode; V
CC
= 4.5 V;
V
rH
= 3 V; V
rL
= 1.5 V
PAST mode; V
CC
= 4.5 V
•
Level conversion
•
Process control (temperature,
pressure, power e.g.)
•
Accurate level detectors
•
Time delays
•
Overvoltage, overcurrent
protection
•
Bargraph display with LED’s
•
Battery charge control
•
Analog to digital conversion
DESCRIPTION
The 74HC/HCT7132 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT7132 contain 4
comparators with two common
74HC/HCT7132
reference inputs V
rH
and V
rL
and four
separate signal inputs V
in0
to V
in3
.
The circuits can be applied in two
modes:
1. The PAST (precision adjustable
Schmitt-trigger) mode at which a
voltage level equal to the wanted
V
T+
must be applied to the
V
rH
input and a voltage level
equal to the wanted V
T−
to the
V
rL
input.
2. The comparator mode at which
the V
rL
input must be connected
to GND and the V
rH
input is the
active reference level input. In
this mode a few resistors must be
added to achieve a small
hysteresis in order to avoid
oscillations. The operation in both
modes will be further explained
by means of the logic diagram of
Fig.5.
TYPICAL
1.15 to V
CC
−
1.2
0.6 to V
CC
1.10 to V
CC
−
1.25
±20
100
30
8
180
40/60
UNIT
V
V
V
mV
pF
pF
mW
ns
ns
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger /
comparator with output latches; 3-state
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
74HC/HCT7132P
74HC/HCT7132T
PINNING
PIN
1, 6, 8, 13
2
3, 5, 10, 12
4
7
9
11
14
OE
V
in0
to V
in3
V
rL
GND
LE
V
rH
V
CC
SYMBOL
Q
0
to Q
3
14
14
PIN POSITION
DIL
SO
74HC/HCT7132
MATERIAL
plastic
plastic
CODE
SOT27
SOT108
NAME AND FUNCTION
3-state latch outputs
3-state output enable input (active LOW)
signal inputs
low reference voltage input
ground (0 V)
latch enable input (active HIGH)
high reference voltage input
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger /
comparator with output latches; 3-state
Table 1
Function table for PAST mode
LE
L
L
L
L
LE
L
L
L
H
X
L
L
L
L
H
L
L
L
L
OE
L
H
H
Q
t-1
Z
OE
H
H
L
L
Q
n
Q
n
The latch
74HC/HCT7132
V
inn
(rising edge)
V
inn
<
V
LL
V
LL
<
V
inn
<
V
rH
V
HH
>
V
inn
>
V
rH
V
inn
>
V
HH
V
inn
(falling edge)
V
HH
>
V
inn
>
V
rL
V
LL
<
V
inn
<
V
rL
V
inn
<
V
LL
V
inn
= X
V
inn
= X
Note
The output information can be stored in a latch on
activating the LE input. In the PAST mode this latch is also
used to control the reference input of the comparator which
is either connected to the V
rH
input via SW
1
or to the
V
rL
input via SW
2
. In case of the comparator mode the
reference input is always connected to the V
rH
input. This
is done by means of an AND gate.
The exclusive OR gate
By means of this function the output stage is switched
between inverting and non-inverting. In the PAST mode
the inverting output of the mode selector is “1” so the
exclusive OR is inverting. In the comparator mode this
output is “0” so the exclusive OR is non-inverting.
The operation in the PAST mode
The operation in the PAST mode will be further outlined
with the aid of Fig.5 and 9. and Table 1. When the level of
V
INn
is 0 V the power of the comparator is switched OFF
and the output circuit is controlled by the digital detector
which output is LOW in that situation. So the output of the
transparent latch is LOW. As the output stage is inverting
now Q
n
is HIGH. In this condition the reference input of the
comparator is connected to the
+V
rH
input. When starting
from 0 V the level at V
inn
is increased, at about the
V
LL
level (≈1 V) the DC power of the comparator is
switched ON. The control of the output circuit is switched
over from the digital detector output to the comparator
output, when after a delay the voltage at this node is
stabilised. During this operation the output level of the
latch output remains LOW and the level of Q
n
HIGH. When
the level at V
inn
reaches the V
rH
level the output level of the
comparator turns to HIGH and so the output level of the
transparent latch. The level at Q
n
turns to LOW. In this
instant the reference input of the comparator is switched
over from V
rH
to V
rL
leaving the output voltage at
Q
n
constant. When the level at V
inn
reaches the V
HH
level
(≈ V
CC
−
1 V) the DC power of the comparator is switched
OFF. The control of the output circuit is switched over from
the comparator output to the digital detector output which
voltage level is HIGH in this situation. During this action the
level at Q
n
remains LOW. When the level at the V
inn
input
is decreased starting at V
CC
level, at the V
HH
level
(≈V
CC
−
1 V) the power of the comparator will be switched
on again. The control of the output circuit is switched over
from the digital detector output to the comparator output
when after a delay the voltage at this node is stabilised. As
the comparator output level is HIGH in this situation the
output level of the latch remains HIGH and the Q
n
output
LOW. When the level at V
inn
reaches the V
rL
level the
4
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
Q
t−1
= initial state
DETAILED DESCRIPTION
The mode selector.
See Fig.5 for logic diagram. The circuit can be applied in
two modes that are selected by the mode selector on
bases of the level on the V
rL
input. When the level on this
input is in the operating area of the PAST mode (V
rL
>
1 V)
the true output of the mode detector is “0“ which means
that the PAST mode is selected. When the V
rL
input is at
GND level the true output of the mode detector is “1” by
which the comparator mode is selected. This mode needs
only one reference input being the V
rH
input.
The Power-on Detector
The power-on detector selects a window typically between
V
INn
= 1 V and V
INn
= V
CC
−
1 V in which in case of the
PAST mode the power of the analog part (comparator) is
switched on. When operating in the comparator mode the
power is always switched on by means of an OR gate.
The digital detector
The digital detector is a Flip-Flop which output is set to
LOW when V
INn
<
1 V and to HIGH when
V
INn
>
V
CC
−
1 V. This detector controls the output stage in
the cases that the power of the comparator is switched off.
This is performed by means of the switches SW
3
and SW
4
.
September 1993
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger /
comparator with output latches; 3-state
output level of the comparator turns to LOW and so the
output level of the transparent latch. The level at Q
n
turns
to HIGH. In this instant the reference input of the
comparator is switched over from V
rL
to V
rH
leaving the
output voltage at Q
n
constant. When the level at
V
inn
reaches about 1 V the DC power of the comparator is
switched OFF again. The control of the output circuit is
switched over from the comparator output to the digital
detector output which voltage level is LOW in this situation.
During this action the level at Q
n
remains HIGH. The
function of the circuit is a Schmitt-trigger of which the
V
T+
and V
T−
levels can be set at the V
rH
and V
rL
inputs.
These levels can be varied from
≈1
V up to
≈V
CC
−
1 V. so
the maximum obtainable hysteresis is
≈V
CC
−
2 V. The
on-and off switching of the power and the stabilization of
the comparator needs time, therefore the minimum
applicable rise- and fall time of the input signal are limited
when the maximum accuracy is required. When during the
rise time of the input signal the input level has past the
V
LL
level, the power starts to switch on. Only when the
comparator is stable at the moment that the input signal
passes the V
rH
level the comparator has its true delay and
its optimal accuracy. When the V
rH
level is passed before
the comparator is stable an extra delay occurs due to the
switching of the power and the accuracy of the comparator
is less. At the positive going edge, this extra delay
depends on the difference between V
LL
and V
rH
and the
rise time of the signal. This is shown in Fig.8, where by
means of curves A and B t
PHL
is plotted at V
rH
is 1.15 V
and 2.25 V respectively and V
CC
= 4.5 V. As with curve a
V
rH
is very close to V
LL
the part of the input edge that is
available for switching the power on is very small. This
causes that only at a rise time
>
500 ns/V the delay will be
equal to the true delay of the comparator. At V
rH
= 2.25 V
this situation is reached already at a rise time of 120 ns/V.
At a very short rise time, the major part of the propagation
delay is due to the switching time of the power. At the
negative going edge, the power is switched on when the
level V
HH
is passed so the extra delay depends on the
difference between V
HH
and V
rL
and the fall time of the
signal. This situation is referred to with curves C and D
where t
PLH
is drawn against the fall time of the input signal.
With curve C V
rL
is 3.25 V which is on the edge of the
operating region. Curve D corresponds with a V
rL
value of
2.25 V. For linear input edges the recommended minimum
rise time at V
CC
= 4.5 V or 6 V is 100 ns/V and at
V
CC
= 3 V, 300 ns/V. For non-linear input signals, during
the rising edge there must be a delay between the time at
which the V
LL
level is passed and the time at which the
V
rH
level is passed. This delay will be dependent on the
V
CC
level and the amplitude of the overdrive of V
LL
. There
is no limitation on the signal slope during the passing of the
levels. For the same reasons, during the falling edge there
September 1993
5
74HC/HCT7132
must be a delay between the time at which the V
HH
level is
passed and the time at which the V
rL
level is passed.
A possible application of the circuit is as precision
oscillator see Fig.6. The operating frequency is:
1
f
=
-----------------------------------------------------------
-
t
RC
+
2
× (
t
PLH
+
t
PHL
)
V
CC
–
V
rL
where t
RC
=
2
×
In
-------------------------
×
RC
-
V
CC
–
V
rH
The operation in the comparator mode
The IC can be applied as a comparator by connecting the
V
rL
input to GND and adjusting the level at V
rH
to the
wanted detection level see Fig.7. In this mode the DC
power of the comparator is always on and the output stage
is set to non-inverting. The function table for this operation
mode is given in table 2.
Table 2
Function table for Comparator mode
LE
L
L
H
X
L
L
L
H
OE
L
H
Q
n-1
Z
Q
n
INPUT
V
inn
<
V
ref
V
inn
>V
ref
V
inn
= X
V
inn
= X
Notes
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
The fact that the power is always on offers the feature of a
more extended operation region of the V
rH
input voltage
which is at a V
CC
of 4.5 V from 1.1 V up to 4.2 V see also
Fig.12. A hysteresis of about 50 mV is required to
overcome oscillations. This has to be performed by means
of a few external resistors. The DC power in this operation
mode at V
CC
= 4.5 V is typical 2 mW per function. A curve
showing t
PD
as a function of the overdrive is given in
Fig.11. A possible diagram for a bargraph display is shown
in Fig.10.
FPGA/CPLD
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