AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14
| 参数名称 | 属性值 |
| 厂商名称 | Cobham PLC |
| 包装说明 | DFP, FL14,.3 |
| Reach Compliance Code | unknown |
| ECCN代码 | 3A001.A.1.A |
| 系列 | ACT |
| JESD-30 代码 | R-XDFP-F14 |
| JESD-609代码 | e4 |
| 长度 | 9.525 mm |
| 负载电容（CL） | 50 pF |
| 逻辑集成电路类型 | AND GATE |
| 最大I（ol） | 0.008 A |
| 功能数量 | 3 |
| 输入次数 | 3 |
| 端子数量 | 14 |
| 最高工作温度 | 125 °C |
| 最低工作温度 | -55 °C |
| 封装主体材料 | CERAMIC, METAL-SEALED COFIRED |
| 封装代码 | DFP |
| 封装等效代码 | FL14,.3 |
| 封装形状 | RECTANGULAR |
| 封装形式 | FLATPACK |
| 电源 | 5 V |
| Prop。Delay @ Nom-Sup | 13 ns |
| 传播延迟（tpd） | 13 ns |
| 认证状态 | Qualified |
| 施密特触发器 | NO |
| 筛选级别 | 38535V;38534K;883S |
| 座面最大高度 | 2.921 mm |
| 最大供电电压 (Vsup) | 5.5 V |
| 最小供电电压 (Vsup) | 4.5 V |
| 标称供电电压 (Vsup) | 5 V |
| 表面贴装 | YES |
| 技术 | CMOS |
| 温度等级 | MILITARY |
| 端子面层 | GOLD |
| 端子形式 | FLAT |
| 端子节距 | 1.27 mm |
| 端子位置 | DUAL |
| 总剂量 | 1M Rad(Si) V |
| 宽度 | 6.2865 mm |
| Base Number Matches | 1 |
| 5962H9652301VXC | 5962H9652301QXC | 5962H9652301VCC | 5962H9652301QXA | 5962H9652301VCA | 5962H9652301QCA | 5962H9652301QCC | |
|---|---|---|---|---|---|---|---|
| 描述 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 | AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 |
| 包装说明 | DFP, FL14,.3 | DFP, FL14,.3 | DIP, DIP14,.3 | DFP, FL14,.3 | DIP, DIP14,.3 | DIP, DIP14,.3 | SIDE BRAZED, CERAMIC, DIP-14 |
| Reach Compliance Code | unknown | unknown | unknown | unknown | unknown | unknown | unknown |
| ECCN代码 | 3A001.A.1.A | 3A001.A.1.A | 3A001.A.1.A | 3A001.A.1.A | 3A001.A.1.A | 3A001.A.1.A | 3A001.A.1.A |
| 系列 | ACT | ACT | ACT | ACT | ACT | ACT | ACT |
| JESD-30 代码 | R-XDFP-F14 | R-XDFP-F14 | R-XDIP-T14 | R-XDFP-F14 | R-XDIP-T14 | R-XDIP-T14 | R-XDIP-T14 |
| JESD-609代码 | e4 | e4 | e4 | e0 | e0 | e0 | e4 |
| 长度 | 9.525 mm | 9.525 mm | 19.43 mm | 9.525 mm | 19.43 mm | 19.43 mm | 19.43 mm |
| 负载电容（CL） | 50 pF | 50 pF | 50 pF | 50 pF | 50 pF | 50 pF | 50 pF |
| 逻辑集成电路类型 | AND GATE | AND GATE | AND GATE | AND GATE | AND GATE | AND GATE | AND GATE |
| 最大I（ol） | 0.008 A | 0.008 A | 0.008 A | 0.008 A | 0.008 A | 0.008 A | 0.008 A |
| 功能数量 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| 输入次数 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| 端子数量 | 14 | 14 | 14 | 14 | 14 | 14 | 14 |
| 最高工作温度 | 125 °C | 125 °C | 125 °C | 125 °C | 125 °C | 125 °C | 125 °C |
| 最低工作温度 | -55 °C | -55 °C | -55 °C | -55 °C | -55 °C | -55 °C | -55 °C |
| 封装主体材料 | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED | CERAMIC, METAL-SEALED COFIRED |
| 封装代码 | DFP | DFP | DIP | DFP | DIP | DIP | DIP |
| 封装等效代码 | FL14,.3 | FL14,.3 | DIP14,.3 | FL14,.3 | DIP14,.3 | DIP14,.3 | DIP14,.3 |
| 封装形状 | RECTANGULAR | RECTANGULAR | RECTANGULAR | RECTANGULAR | RECTANGULAR | RECTANGULAR | RECTANGULAR |
| 封装形式 | FLATPACK | FLATPACK | IN-LINE | FLATPACK | IN-LINE | IN-LINE | IN-LINE |
| 电源 | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Prop。Delay @ Nom-Sup | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns |
| 传播延迟（tpd） | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns | 13 ns |
| 认证状态 | Qualified | Qualified | Qualified | Qualified | Qualified | Qualified | Qualified |
| 施密特触发器 | NO | NO | NO | NO | NO | NO | NO |
| 筛选级别 | 38535V;38534K;883S | 38535Q/M;38534H;883B | 38535V;38534K;883S | 38535Q/M;38534H;883B | 38535V;38534K;883S | 38535Q/M;38534H;883B | 38535Q/M;38534H;883B |
| 座面最大高度 | 2.921 mm | 2.921 mm | 5.08 mm | 2.921 mm | 5.08 mm | 5.08 mm | 5.08 mm |
| 最大供电电压 (Vsup) | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V |
| 最小供电电压 (Vsup) | 4.5 V | 4.5 V | 4.5 V | 4.5 V | 4.5 V | 4.5 V | 4.5 V |
| 标称供电电压 (Vsup) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| 表面贴装 | YES | YES | NO | YES | NO | NO | NO |
| 技术 | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| 温度等级 | MILITARY | MILITARY | MILITARY | MILITARY | MILITARY | MILITARY | MILITARY |
| 端子面层 | GOLD | GOLD | GOLD | TIN LEAD | TIN LEAD | TIN LEAD | GOLD |
| 端子形式 | FLAT | FLAT | THROUGH-HOLE | FLAT | THROUGH-HOLE | THROUGH-HOLE | THROUGH-HOLE |
| 端子节距 | 1.27 mm | 1.27 mm | 2.54 mm | 1.27 mm | 2.54 mm | 2.54 mm | 2.54 mm |
| 端子位置 | DUAL | DUAL | DUAL | DUAL | DUAL | DUAL | DUAL |
| 总剂量 | 1M Rad(Si) V | 1M Rad(Si) V | 1M Rad(Si) V | 1M Rad(Si) V | 1M Rad(Si) V | 1M Rad(Si) V | 1M Rad(Si) V |
| 宽度 | 6.2865 mm | 6.2865 mm | 7.62 mm | 6.2865 mm | 7.62 mm | 7.62 mm | 7.62 mm |
| Base Number Matches | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
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EE_FPGA学习乐园
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