INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT257
Quad 2-input multiplexer; 3-state
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Sep 30
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
FEATURES
•
Non-inverting data path
•
3-state outputs interface directly with system bus
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT257 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT257 have four identical 2-input multiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
74HC/HCT257
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The “257” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE.(1I
1
.S
+
1I
0
.S)
2Y = OE.(2I
1
.S
+
2I
0
.S)
3Y = OE.(3I
1
.S
+
3I
0
.S)
4Y = OE.(4I
1
.S
+
4I
0
.S)
The “257” is identical to the “258” but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nI
0
, nI
1
to nY
S to nY
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
input capacitance
power dissipation capacitance per multiplexer notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
14
3.5
45
13
17
3.5
45
ns
ns
pF
pF
HCT
UNIT
1998 Sep 30
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
ORDERING INFORMATION
TYPE
NUMBER
74HC257N;
74HCT257N
74HC257D;
74HCT257D
74HC257DB;
74HCT257DB
74HC257PW;
74HCT257PW
PACKAGE
NAME
DIP16
SO16
SSOP16
TSSOP16
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT257
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
SYMBOL
S
1I
0
to 4I
0
1I
1
to 4I
1
1Y to 4Y
GND
OE
V
CC
NAME AND FUNCTION
common data select input
data inputs from source 0
data inputs from source 1
3-state multiplexer outputs
ground (0 V)
3-state output enable input (active LOW)
positive supply voltage
fpage
fpage
1
2
3
5
6
11
10
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
OE
MGA835
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
16 VCC
15 OE
14 4I0
S
1Y
4
257
5
6
7
8
MLB311
13 4I1
12 4Y
11 3I0
10 3I1
9
3Y
2Y
7
3Y
9
14
13
15
4Y
12
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Sep 30
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
FUNCTION TABLE
INPUTS
OE
2
3
5
6
11
10
14
13
1I0 1I1
2I0 2I1
3I0 3I1
4I0 4I1
74HC/HCT257
OUTPUT
nI
1
X
L
H
X
X
nY
Z
L
H
L
H
S
X
H
H
L
L
nI
0
X
X
X
L
H
H
L
1 S
SELECTOR
L
L
L
15 OE
3-STATE MULTIPLEXER OUTPUTS
1Y
4
2Y
7
3Y
12
4Y
9
MGR280
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
1998 Sep 30
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
74HC/HCT257
TEST CONDITIONS
UNIT
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
+25
−40
to
+85
−40
to
+125
min.
max.
165
33
28
225
45
38
225
45
38
225
45
38
90
18
15
min. typ. max. min. max.
t
PHL
/ t
PLH
propagation delay
nI
0
to nY;
nI
1
to nY
t
PHL
/ t
PLH
propagation delay
S to nY
36
13
10
47
17
14
33
12
10
41
15
12
14
5
4
110
22
19
150
30
26
150
30
26
150
30
26
60
12
10
140
28
24
190
38
33
190
38
33
190
38
33
75
15
13
ns
t
PZH
/ t
PZL
3-state output enable time
OE to nY
t
PHZ
/ t
PLZ
3-state output disable time
OE to nY
t
THL
/ t
TLH
output transition time
1998 Sep 30
5
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