(8K x 16-Bit) Dual Port RAM
High-Speed CMOS
7025E
Memory
Logic Diagram
F
EATURES
:
• 8K x 16-bit dual port RAM
- Stand Alone
- Master Slave
• R
AD
-P
AK
® radiation-hardened against natural space
radiation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
-SEL
TH
LET = >100 MeV/mg/cm
2
-SEU
TH
LET = 7 MeV/mg/cm
2
• Package:
-84 Pin R
AD
-P
AK
® quad flat pack
• Separate upper byte and lower byte control for multiplexed
bus compatibility
• High speed access time: 35/45 ns
• Expandable to 32 bits or more using master/slave select
when cascading
• High speed CMOS technology
-TTL compatible, single 5V power supply
-Interrupt flag for port-to-port communication
-On chip port arbitration logic
-Asynchronous operation from either port
D
ESCRIPTION
:
Maxwell Technologies’ 7025E Dual Port RAM High Speed
CMOS® microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. The 7025E is
designed to be used as a stand-alone 128k-bit Dual Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-
bit or more word systems. This design results in full-speed,
error-free operation without the need for additional discrete
logic. The 7025E provides two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CS
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
08.15.02 Rev 2
All data sheets are subject to change without notice
1
(619) 503-3300- Fax: (619) 503-3301- www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
T
ABLE
1. 7025E P
INOUT
D
ESCRIPTION
N
AMES
Chip Select
Read/Write Select
Output Select
Address
Data Input/Output
Semaphore Select
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
M/S
V
CC
GND
L
EFT
P
ORT
CS
L
R/W
L
OS
L
AO
L
-A12
L
I/OO
L
-I/O15
L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
R
IGHT
P
ORT
CS
R
R/W
R
OS
R
AO
R
-A12
R
I/OO
R
-I/O15
R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Master or Slave Select
Power
Ground
7025E
Memory
T
ABLE
2. 7025E A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply Voltage (Relative to V
SS
)
Operating Temperature Range
Input or Output Voltage Applied
Storage Temperature Range
S
YMBOL
V
CC
T
A
--
T
STG
M
IN
-0.3
-55
GND -0.3V
-65
M
AX
7.0
125
V
CC
+ 0.3
150
U
NITS
V
°
C
V
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CCOP
I
CCOP1
I
CCSB
I
CCSB1
V
ARIATION
± 10% A
S
S
TATED
I T
ABLE
6
± 10% A
S
S
TATED
I T
ABLE
6
± 10% A
S
S
TATED
I T
ABLE
6
± 10% A
S
S
TATED
I T
ABLE
6
T
ABLE
4. 7025E R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage Positive
Input Voltage
S
YMBOL
V
CC
V
IL
V
IH
08.15.02 Rev 2
M
IN
4.5
-0.5
2.2
M
AX
5.5
0.8
6.0
U
NITS
V
V
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
T
ABLE
4. 7025E R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Thermal Impedance
Operating Temperature Range
S
YMBOL
M
IN
--
-55
M
AX
1.02
125
7025E
U
NITS
°C/W
°
C
Θ
JC
T
A
T
ABLE
5. 7025E C
APACITANCE
P
ARAMETER
Input Capacitance: V
IN
= 0V
1
Output Capacitance: V
OUT
= 0V
1
1. Guaranteed by design.
S
YMBOL
C
IN
C
OUT
M
IN
--
--
M
AX
5
7
U
NITS
pF
pF
T
ABLE
6. 7025E DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ± 10%, T
A
= -55
TO
125
°
C
UNLESS OTHERWISE
)
P
ARAMETER
Input Leakage Current
1
Output Leakage Current
2
Standby Supply Current, Both ports TTL level inputs
-35
-45
Standby Supply Current, Both ports CMOS level inputs
-35
-45
Operating Supply Current, Both ports Active
-35
-45
Operating Supply Current, One Port Active, One Port Standby
-35
-45
Input Low Voltage
3
Input High Voltage
Output Low Voltage
4
Output High Voltage
1. VCC = 5.5V, VIN = GND to VCC, CS = VIH, VOUT = 0 to VCC.
2.
Vcc=5.5V; Vout = GND to Vcc
3.
VIH max = VCC + 0.3V, VIL min = -0.3V or -1V pulse width 50 ns
4. V
CC
min, I
OL
= 4 mA, I
OH
= -4 mA.
S
YMBOL
I
LI
I
LO
I
CCSB
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
--
--
1, 2, 3
--
--
1, 2, 3
--
--
1, 2, 3
--
--
1, 2, 3
1, 2, 3
--
2.2
--
2.4
190
180
0.8
--
0.4
--
V
V
320
280
mA
5
5
mA
50
50
mA
M
IN
--
--
M
AX
±10
±10
U
NITS
µA
µA
mA
Memory
I
CCSB1
I
CCOP
I
CCOP1
V
IL
V
IH
V
OL
V
OH
08.15.02 Rev 2
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
T
ABLE
7. 7025E AC E
LECTRICAL
C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 5V ± 10%, V
SS
= 0V, T
A
= -55
TO
125
°
C)
P
ARAMETER
Read Cycle Time
-35
-45
Address Access Time
-35
-45
Chip Select Access Time
1
-35
-45
Byte Select Access Time
1
-35
-45
Output Select to Output Valid
-35
-45
Output Low Z Time
2,3
-35
-45
Output High Z Time
2,3
-35
-45
Chip Enable to Power Up Time
2
Chip Disable to Power Up Time
2
Semaphore Flag Update Pulse (OE or SEM)
S
YMBOL
t
RC
S
UBGROUPS
9, 10, 11
35
45
9, 10, 11
--
--
9, 10, 11
--
--
9, 10, 11
--
--
9, 10, 11
--
--
9, 10, 11
3
3
9, 10, 11
--
--
9, 10, 11
9, 10, 11
9, 10, 11
0
--
15
20
20
--
50
--
--
--
20
25
35
45
35
45
35
45
--
--
M
IN
7025E
M
AX
U
NIT
ns
t
AA
ns
t
ACS
ns
t
ABE
ns
t
AOE
ns
Memory
t
LZ
ns
t
HZ
ns
ns
ns
ns
t
PU
t
PD
t
SOP
1. To access RAM, CS = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CS = V
IN
and SEM = V
IL
. Either condition must be
valid for the entire t
EW
time.
2. Guaranteed by design.
3. Transition is measured ± 500 mV from low or high impedance voltage with load.
T
ABLE
8. 7025E AC E
LECTRICAL
C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
= 5V ± 10%, V
SS
= 0V, T
A
= -55
TO
125
°
C)
P
ARAMETER
Write Cycle Time
-35
-45
Address Valid to End of Write
-35
-45
08.15.02 Rev 2
S
YMBOL
t
WC
S
UBGROUPS
9, 10, 11
M
IN
35
45
M
AX
--
--
U
NIT
ns
t
AW
9, 10, 11
30
40
--
--
ns
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
T
ABLE
8. 7025E AC E
LECTRICAL
C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
= 5V ± 10%, V
SS
= 0V, T
A
= -55
TO
125
°
C)
P
ARAMETER
Chip Select to End of Write
1
-35
-45
Address Setup Time
-35
-45
Write Pulse Width
-35
-45
Write Recovery Time
-35
-45
Data Valid to End of Write
-35
-45
Output High Z Time
2,3
-35
-45
Data Hold Time
-35
-45
Write Select to Output in High Z
2,3
-35
-45
Output Active from End of Write
-35
-45
SEM Flag Write to Read Time
-35
-45
SEM Flag Contention Window
-35
-45
2,3,4
7025E
S
UBGROUPS
9, 10, 11
30
40
9, 10, 11
0
0
9, 10, 11
30
35
9, 10, 11
0
0
9, 10, 11
25
25
9, 10, 11
--
--
9, 10, 11
0
0
9, 10, 11
--
--
9, 10, 11
0
0
10
10
10
10
--
--
ns
--
--
ns
--
--
20
20
ns
--
--
ns
20
20
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
M
IN
M
AX
U
NIT
ns
S
YMBOL
t
SW
t
AS
t
WP
t
WR
t
DW
Memory
t
HZ
t
DH
t
WZ
t
OW
t
SWRD
t
SPS
1. To access RAM, CS = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CS = V
IN
and SEM = V
IL
. Either condition must be
valid for the entire t
EW
time.
2. Guaranteed by design.
3. Transition is measured ± 500 mV from low or high impedance voltage with load.
4. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
DW
.
08.15.02 Rev 2
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
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