CD54HC670, CD74HC670,
CD74HCT670
Data sheet acquired from Harris Semiconductor
SCHS195C
January 1998 - Revised October 2003
High-Speed CMOS Logic
4x4 Register File
Description
The ’HC670 and CD74HCT670 are 16-bit register files
organized as 4 words x 4 bits each. Read and write address
and enable inputs allow simultaneous writing into one location
while reading another. Four data inputs are provided to store
the 4-bit word. The write address inputs (WA0 and WA1)
determine the location of the stored word in the register.
When write enable (WE) is low the word is entered into the
address location and it remains transparent to the data. The
outputs will reflect the true form of the input data. When (WE)
is high data and address inputs are inhibited. Data acquisition
from the four registers is made possible by the read address
inputs (RA1 and RA0). The addressed word appears at the
output when the read enable (RE) is low. The output is in the
high impedance state when the (RE) is high. Outputs can be
tied together to increase the word capacity to 512 x 4 bits.
Features
[ /Title
(CD74H
C670,
CD74H
CT670)
/Subject
(High-
Speed
CMOS
Logic
4x4 Reg-
ister
• Simultaneous and Independent Read and Write
Operations
• Expandable to 512 Words of n-Bits
• Three-State Outputs
• Organized as 4 Words x 4 Bits Wide
• Buffered Inputs
• Typical Read Time = 16ns for ’HC670 V
CC
= 5V, C
L
=
15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC670F3A
CD74HC670E
CD74HC670M
CD74HC670MT
CD74HC670M96
CD74HCT670E
CD74HCT670M
CD74HCT670MT
CD74HCT670M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC670
(CERDIP)
CD74HC670, CD74HCT670
(PDIP, SOIC)
TOP VIEW
D1 1
D2 2
D3 3
RA1 4
RA0 5
Q3 6
Q2 7
GND 8
16 V
CC
15 D0
14 WA0
13 WA1
12 WE
11 RE
10 Q0
9 Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD54HC670, CD74HC670, CD74HCT670
Functional Diagram
15
D0
D1
D2
D3
WE
RE
RA1
RA0
WA0
WA1
4
5
14
13
1
2
3
12
11
10
9
7
6
Q0
Q1
Q2
Q3
WRITE MODE SELECT TABLE
INPUTS
OPERATING
MODE
Write Data
WE
L
L
Data Latched
NOTE:
1. The Write Address (WA0 and WA1) to the “internal latches” must
be stable while WE is LOW for conventional operation.
H
D
N
L
H
X
INTERNAL
LATCHES
(NOTE 1)
L
H
No Change
Disabled
NOTE:
READ MODE SELECT TABLE
INPUTS
OPERATING
MODE
Read
INTERNAL
LATCHES
(NOTE 2)
L
H
X
OUTPUT
Q
N
L
H
(Z)
RE
L
L
H
2. The selection of the “internal latches” by Read Address (RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State
2
CD54HC670, CD74HC670, CD74HCT670
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3)
θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-6
-7.8
0.02
0.02
0.02
-
6
7.8
-
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
3
CD54HC670, CD74HC670, CD74HCT670
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
Three- State Leakage
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Three- State Leakage
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
4. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
∆I
CC
(Note 4)
I
I
I
CC
V
CC
and
GND
V
CC
or
GND
V
IL
or V
IH
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
V
IL
or V
IH
I
O
(mA)
0
V
O
=
V
CC
or
GND
25
o
C
MIN
-
-
TYP
-
-
MAX
8
±0.5
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
-
-
MAX
80
±5.0
MIN
-
-
MAX
160
±10
UNITS
µA
µA
V
CC
(V)
6
6
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
V
O
=
V
CC
or
GND
-
5.5
5.5
5.5
-
-
-
-
-
±0.1
8
±0.5
-
-
-
±1
80
±5.0
-
-
-
±1
160
±10
µA
µA
µA
V
CC
-2.1
4.5 to
5.5
-
100
360
-
450
-
490
µA
HCT Input Loading Table
INPUT
WE
WA0
WA1
RE
DATA
RA0
RA1
UNIT LOADS
0.3
0.2
0.4
1.5
0.15
0.4
0.7
NOTE: Unit Load is
∆I
CC
limit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25
o
C.
4
CD54HC670, CD74HC670, CD74HCT670
Prerequisite for Switching Specifications
25
o
C
PARAMETER
HC TYPES
Setup Time
Data to WE
Write to WE
t
SU
, t
h
2
4.5
6
Hold Time
Data to WE
Write to WE
t
H
, t
W
2
4.5
6
Pulse Width WE
t
W
2
4.5
6
Latch Time WE to RA0,
RA1
t
LATCH
2
4.5
6
HCT TYPES
Setup Time
Data to WE
Hold Time
Data to WE
Write to WE
Setup Time
Write to WE
Pulse Width WE
Latch Time WE to RA0,
RA1
t
SU
, t
h
t
H
, t
W
4.5
12
-
-
15
-
-
18
-
-
ns
60
12
10
5
5
5
80
16
14
100
20
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
15
13
5
5
5
100
20
17
125
25
21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
18
15
5
5
5
120
24
20
150
30
26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO 85
o
C
MIN
TYP
MAX
-55
o
C TO 125
o
C
MIN
TYP
MAX
UNITS
4.5
5
-
-
5
-
-
5
-
-
ns
t
SU
t
W
t
LATCH
4.5
18
-
-
23
-
-
27
-
-
ns
4.5
4.5
20
25
-
-
-
-
25
31
-
-
-
-
30
38
-
-
-
-
ns
ns
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
25
o
C
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO
85
o
C
MIN
MAX
-55
o
C TO
125
o
C
MIN
MAX
UNITS
PARAMETER
HC TYPES
Propagation Delay
Reading Any Word
SYMBOL
TEST
CONDITIONS
t
PLH
, t
PHL
C
L
= 50pF
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
-
-
-
-
-
-
-
-
-
-
16
-
-
-
21
-
195
39
-
33
250
50
-
43
-
-
-
-
-
-
-
-
245
49
-
42
315
63
-
54
-
-
-
-
-
-
-
-
295
59
-
50
375
75
-
64
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable to Output
t
PLH
, t
PHL
C
L
= 50pF
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
