E2U0037-28-82
¡ Semiconductor
MSM7602
¡ Semiconductor
Echo Canceler
This version: Aug. 1998
MSM7602
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7602 is an improved version of the MSM7520 with the same basic configuration. The
MSM7602 uses a 19.2 MHz clock frequency to meet PHS, the 3 V power supply (2.7 V to 5.5 V),
and compact packaging. Also, this device adds the howling detecter control pins and main clook
output pins. (See the Appendix)
The MSM7602 is a low-power CMOS IC device for canceling echo (in an acoustic system or
telephone line) generated in a speech path.
Echo is canceled, in digital signal processing, by estimating the echo path and generating a
pseudo echo signal.
When used as an acoustic echo canceler, the device cancels the acoustic echo between the loud
speaker and the microphone which occurs during hands free communication such as with a
cellular phone or a conference system phone.
When used as a line echo canceler, the device cancels the line echo caused by impedance
mismatching in a hybrid.
In addition, the MSM7602 makes possible a quality conversation by controlling the noise level
and preventing howling with howling detector, double talk detector, attenuation function, and
a gain control function. The devise also controls the low level noise with a center clipping
function.
Further, the MSM7602 I/O interface supports
m-law
PCM . The use of a single chip CODEC, such
as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows an economic and efficient echo
canceler configuration.
FEATURES
• Handles both acoustic echoes and telephone line echoes.
• Cancelable echo delay time:
MSM7602-001 ................. For a single chip: 23 ms (max.)
MSM7602-011 ................. For a cascade connection (can also be used for a single chip)
Master chip: 23 ms (max.)
Slave chip: 31 ms (max.)
Cancelable up to 209 ms (1 master plus 6 slaves)
For a single chip: 23 ms (max.)
• Echo attenuation
: 30 dB (typ.)
• Clock frequency
: 19.2 MHz
External input and internal oscillator circuit are provided.
• Power supply voltage : 2.7 V to 5.5 V
• Package options:
28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7602-001GS-K)
56-pin plastic QFP
(QFP56-P-910-0.65-2K) (Product name : MSM7602-011GS-2K)
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¡ Semiconductor
MSM7602
BLOCK DIAGRAM
MSM7602-001 (Single chip only)
RIN
S/P
Non–linear/
Linear
ATT
Gain
Linear/
Non–linear
P/S
ROUT
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
–
SOUT
WDT
PWDWN
MCKO
X1/CLKIN
X2 SCKO SYNCO
NLP HCL ADP ATT GC
HD
* Clock Generator
Mode Selector
P/S
Linear/
Non–linear
Center
Clip
ATT
+
+
Non–linear/
Linear
S/P
SIN
RST
V
DD
I/O Controller
V
SS
INT IRLD
SCK SYNC
MSM7602-011 (Cascade connection or single chip)
RIN
S/P
Non–linear/
Linear
ATT
Gain
Howling
Detector
Double Talk
Detector
Power
Calculator
SOUT
WDT
*
PWDWN
MCKO
P/S
Linear/
Non–linear
Center
Clip
ATT
* Clock Generator
Mode Selector
X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC MS HD
INT IRLD
SCK SYNC
*
*
*
*
* If the MSM7602-011 is used in the slave mode, only the diagonally hatched blocks and
the pins marked with * are used.
,
Linear/
Non–linear
P/S
ROUT
Adaptive
FIR Filter
(AFF)
Parallel
I/O Port
PD15 *
PD 0 *
OF1
*
OF2
*
SF1
*
SF2
*
SIN
–
–
Parallel
I/O
Controller
+
+
Non–linear/
Linear
S/P
RST
*
V
DD
*
V
SS
*
I/O Controller
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¡ Semiconductor
MSM7602
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin Plastic SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Pin
1
2
3
4
5
6
7
Symbol
NLP
HCL
ADP
V
DD
ATT
INT
IRLD
Pin
8
9
10
11
12
13
14
Symbol
SIN
RIN
SCK
SYNC
SOUT
ROUT
V
SS
Pin
15
16
17
18
19
20
21
Symbol
V
SS
HD
X1/CLKIN
X2
V
DD
PWDWN
V
SS
Pin
22
23
24
25
26
27
28
Symbol
SYNCO
SCKO
RST
WDT
GC
V
DD
MCKO
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¡ Semiconductor
MSM7602
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-Pin Plastic QFP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol
NLP
HCL
ADP
MS
ATT
INT
IRLD
SIN
RIN
SCK
SYNC
SOUT
ROUT
V
SS
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
PD0
PD1
PD2
PD3
PD4
PD5
V
SS
PD6
PD7
PD8
PD9
PD10
PD11
HD
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
PD12
PD13
X1/CLKIN
X2
V
DD
PWDWN
V
SS
SYNCO
SCKO
RST
WDT
GC
V
DD
V
DD
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
*
PD14
PD15
MCKO
SF2
OF1
V
SS
*
V
SS
SF1
OF2
V
DD
V
DD
*
*: No connect pin
4/29
¡ Semiconductor
MSM7602
PIN DESCRIPTIONS
(1/5)
Pin
28-pin 56-pin
SSOP
1
QFP
1
NLP
I
Control pin for the center clipping function.
This pin forces the SOUT output to a minimum value when the SOUT
signal is below –54 dBm0. Effective for reducing low-level noise.
• Single Chip or Master Chip in a Cascade Connection
"H": Center clip ON
"L": Center clip OFF
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT
signal or the rising edge of the
RST
signal.
Through mode control.
When this pin is in the through mode,
RIN and SIN data is output to ROUT and SOUT. At the same time, the
coefficient of the adaptive FIR filter is cleared.
• Single Chip or Master Chip in a Cascade Connection
"H": Through mode
"L": Normal mode (echo canceler operates)
• Slave Chip in a Cascade Connection
Same as master
This input signal is loaded in synchronization with the falling edge of the
INT
signal or the rising edge of the
RST
signal.
AFF coefficient control.
This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets
the coefficient to a fixed value, when this pin is configured to be the
coefficient fix mode.
This pin is used when holding the AFF coefficient which has been once
converged.
• Single Chip or Master Chip in a Cascade Connection
"H": Coefficient fix mode
"L": Normal mode (coefficient update)
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT
signal or the rising edge of the
RST
signal.
Select signal.
This pin selects between the master chip and slave chip when
used in a cascade connection.
"L": Single chip or master chip
"H": Slave chip
Symbol
Type
Description
2
2
HCL
I
3
3
ADP
I
—
4
MS
I
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