Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
Radiation performance
- Intrinsic total-dose: 300 Krad(Si)
- SEL Immune >100 MeV-cm
2
/mg
- LET
th
(0.25): 53.0 MeV-cm
2
/mg
- Memory Cell Saturated Cross Section 1.67E-7cm
2
/bit
- Neutron Fluence: 3.0E14n/cm
2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup 1.0E11 rad(Si)/sec
Packaging options:
- 68-lead ceramic quad flatpack (20.238 grams with lead
frame)
Standard Microcircuit Drawing 5962-04227
- QML compliant part
INTRODUCTION
The UT8CR512K32 is a high-performance CMOS static RAM
multi-chip module (MCM), organized as four individual
524,288 words by 8 bit SRAMs with common output enable.
Easy memory expansion is provided by active LOW chip
enables (E), an active LOW output enable (G), and three-state
drivers. This device has a power-down feature that reduces
power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking the
corresponding chip enable (E) input LOW and write enable (W)
input LOW. Data on the I/O pins is then written into the location
specified on the address pins (A
0
through A
18
). Reading from
the device is accomplished by taking the chip enable (E) and
output enable (G) LOW while forcing write enable (W) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (E HIGH), the outputs are disabled (G
HIGH), or during a write operation (E LOW and W LOW).
Perform 8, 16, 24 or 32 bit accesses by making W along with E
a common input to any combination of the discrete memory die.
E3
A(18:0)
G
W3
E2
W2
E1
W1
W0
E0
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
Figure 1. UT8CR512K32 SRAM Block Diagram
1
V
DD1
A0
A1
A2
A3
A4
A5
E2
V
SS
E3
W0
A6
A7
A8
A9
A10
V
DD2
DEVICE OPERATION
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
V
SS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
V
SS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
68 67 66 65 64 63 62 61 60 59 58 57 56 555453 52
1
51
2
50
3
49
4
48
5
47
Top View
6
46
7
45
8
44
9
43
10
42
11
41
12
40
13
39
14
38
15
37
16
36
17
35
1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
DD2
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W1
W2
W3
A18
V
DD1
V
SS
Each die in the UT8CR512K32 has three control inputs called
Enable (E), Write Enable (W), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (E) controls device selection,
active, and standby modes. Asserting E enables the device,
causes I
DD
to rise to its active value, and decodes the 19 address
inputs to each memory die by selecting the 2,048,000 byte of
memory. W controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
X
1
0
W
X
0
1
1
E
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
Figure 2. 17ns SRAM Pinout 68)
PIN NAMES
A(18:0)
DQ(7:0)
E
W
G
V
DD1
V
DD2
V
SS
Address
Data Input/Output
Enable
Write Enable
Output Enable
Power (1.8V)
Power (3.3V)
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V
IH
(min) with E and G less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
W deasserted. Valid data appears on data outputs DQn(7:0) after
the specified t
AVQV
is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by E going active while G remains asserted, W remains
deasserted, and the addresses remain stable for the entire cycle.
After the specified t
ETQV
is satisfied, the eight-bit word
addressed by A(18:0) is accessed and appears at the data outputs
DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while E is asserted, W is deasserted,
and the addresses are stable. Read access time is t
GLQV
unless
t
AVQV
or t
ETQV
have not been satisfied.
2
WRITE CYCLE
A combination of W less than V
IL
(max) and E less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when W is less
than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by W going high, with E still active. The
write pulse width is defined by t
WLWH
when the write is initiated
by W, and by t
ETWH
when the write is initiated by E. Unless the
outputs have been previously placed in the high-impedance state
by G, the user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQn(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of E or W going inactive. The
write pulse width is defined by t
WLEF
when the write is initiated
by W, and by t
ETEF
when the write is initiated by the E going
active. For the W initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait t
WLQZ
before applying data to the eight bidirectional
pins DQn (7:0) to avoid bus contention.
The UT8CR512K32 SRAM incorporates special design and
layout features which allows operation in a limited radiation
environment.
Table 2. Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
300K
8.9x10
-10
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 10% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
RADIATION HARDNESS
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 2.0V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
V
IN
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
1.7 to 1.9V
3.0 to 3.6V
(C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
0V to V
DD2
4
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to 125°C for (W) screening)
SYMBOL
V
IH
V
IL
V
OL1
V
OH1
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage
current
Short-circuit output current
I
OL
= 8mA,V
DD2
=V
DD2
(min)
I
OH
= -4mA,V
DD2
=V
DD2
(min)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD2
and V
SS
V
O
= V
DD2
and V
SS,
V
DD2
= V
DD2
(max)
G = V
DD2
(max)
V
DD2
= V
DD2
(max), V
O
= V
DD2
V
DD2
= V
DD2
(max), V
O
= V
SS
Inputs : V
IL
= V
SS
+ 0.2V
V
IH
= V
DD2
- 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
- 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V
V
IH
= V
DD2
- 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
- 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
CMOS inputs , I
OUT
= 0
E = V
DD2
-0.2
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
CMOS inputs , I
OUT
= 0
E = V
DD2
- 0.2
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
100
mA
-2
-2
.8*V
DD2
44
21
2
2
CONDITION
MIN
.7*V
DD2
.3*V
DD2
.2*V
DD2
MAX
UNIT
V
V
V
V
pF
pF
µA
µA
I
OS2, 3
-100
+100
mA
I
DD1
(OP
1
)
Supply current operating
@ 1MHz
40
mA
I
DD1
(OP
2
)
Supply current operating
@58.8MHz
I
DD2
(OP
1
)
Supply current operating
@ 1MHz
.35
mA
I
DD2
(OP
2
)
Supply current operating
@58.8MHz
11
mA
I
DD1
(SB)
4
I
DD2
(SB)
4
I
DD1
(SB)
4
I
DD2
(SB)
4
Supply current standby @
0Hz
35
5
35
5
mΑ
µA
mΑ
µA
Supply current standby
A(18:0) @ 58.8MHz
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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