74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 07 — 26 June 2008
Product data sheet
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8-B/JESD36 (2.7 V to 3.6 V)
±24
mA output drive (V
CC
= 3.0 V)
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
I
I
I
I
I
I
I
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GD
74LVC1G74GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP8
VSSOP8
XSON8
XSON8U
XQFN8U
Description
Version
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT765-1
SOT833-1
SOT996-2
SOT902-1
Type number
4. Marking
Table 2.
Marking codes
Marking code
V74
V74
V74
V74
V74
Type number
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GD
74LVC1G74GM
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah757
Q
Q
S
Q
C1
1D
R
001aah758
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC1G74_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 June 2008
2 of 20
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G74
CP
1
8
V
CC
D
2
7
SD
74LVC1G74
CP
D
Q
GND
1
2
3
4
001aab659
8
7
6
5
V
CC
SD
RD
Q
Q
3
6
RD
GND
4
5
Q
001aab658
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74LVC1G74_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 June 2008
3 of 20
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
terminal 1
index area
SD
1
V
CC
8
7
CP
CP
D
Q
GND
1
2
8
7
V
CC
RD
SD
RD
Q
Q
3
4
5
Q
2
6
D
74LVC1G74
3
4
6
5
GND
001aaf641
001aah948
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
CP
D
Q
GND
Q
RD
SD
V
CC
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
Description
7. Functional description
Table 4.
Input
SD
L
H
L
[1]
Function table for asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74LVC1G74_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 June 2008
4 of 20
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Table 5.
Input
SD
H
H
[1]
Function table for synchronous operation
[1]
Output
RD
H
H
CP
↑
↑
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1]
[1][2]
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
+6.5
±50
100
-
300
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
°C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
−0.5
−0.5
-
-
−100
T
amb
=
−40 °C
to +125
°C
[3]
-
−65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 packages: above 55
°C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
−40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC1G74_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 June 2008
5 of 20
嵌入式系统
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