UT54ACS193E
Synchronous 4-Bit Up-Down Dual Clock Counter
July 2013
www.aeroflex.com/Logic
Datasheet
FEATURES
Look-ahead circuitry enhances cascaded counters
Fully synchronous in count modes
Parallel asynchronous load for modulo-N count lengths
Asynchronous clear
m
CRH CMOS process
- Latchup immune
High speed
Low power consumption
Wide power supply operating range of 3.0V to 5.5V
Available QML Q or V processes
16-lead flatpack
UT54ACS193E - SMD 5962-96566
The device is characterized over full HiRel temperature range
of -55
o
C to +125
o
C.
PINOUT
16-Lead Flatpack
TopView
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
DESCRIPTION
The UT54ACS193E is a synchronous 4-bit, reversible up-down
binary counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change
coincident with each other when instructed. Synchronous
operation eliminates the output counting spikes normally
associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of either count input (Up or Down). The direc-
tion of the counting is determined by which count input is pulsed
while the other count input is high.
The counter is fully programmable. The outputs may be preset
to either level by placing a low on the load input and entering
the desired data at the data inputs. The outputs will change to
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counter to be used as modulo-
N divider by simply modifying the count length with the preset
inputs.
A clear input has been provided that forces all outputs to the
low level when a high level is applied. The clear function is
independent of the count and the load inputs.
The counter is designed for efficient cascading without the need
for external circuitry. The borrow output (BO) produces a low-
level pulse while the count is zero and the down input is low.
Similarly, the carry output (CO) produces a low-level pulse
while the count is maximum and the up input is low.
1
FUNCTION TABLE
FUNCTION
Count Up
Count Down
Reset
Load Preset
Input
CLOCK
UP
H
X
X
CLOCK
DOWN
H
X
X
CLR
L
L
H
L
LOAD
H
H
X
L
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
108
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum package power dissipation
permitted @ Tc = +125
o
C
LIMIT
-0.3 to 7.0
-0.3 to V
DD
+0.3
-65 to +150
+175
+300
15
10
3.3
UNITS
V
V
C
C
C
C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
j(max)
- T
c(max)
) /
jc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to +125
UNITS
V
V
C
4
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS193E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55C < T
C
< +125C)
SYMBOL
V
IL
V
IH
I
IN
V
OL
DESCRIPTION
Low-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 3.0V to 5.5V
V
DD
from 3.0V to 5.5V
V
IN
= V
DD
or V
SS
I
OL
= 100A
V
DD
from 3.0V to 5.5V
V
OH
High-level output voltage
3
I
OH
= -100A
V
DD
from 3.0V to 5.5V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
9
(sink)
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
9
(sink)
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
9
(source)
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
9
(source)
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
P
total1
Power dissipation
8, 9
C
L
= 50pF
V
DD
= 4.5V to 5.5V
P
total2
Power dissipation
8, 9
C
L
= 50pF
V
DD
= 3.0V to 3.6V
I
DDQ
Quiescent Supply Current
V
IN
= V
DD
or V
SS
V
DD
from 3.0V to 5.5V
10
0.6
1.4
mW/
MHz
mW/
MHz
A
-6
mA
-8
mA
6
mA
8
mA
-100
100
mA
-200
200
mA
V
DD
-0.25
V
0.7 V
DD
-1
1
0.25
MIN
MAX
0.3 V
DD
UNIT
V
V
A
V
5
FPGA/CPLD
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