PRESETTABLE BCD/DECADE
UP/DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTERS
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421)
Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16
Binary Counter. State changes of the counters are synchronous with the
LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the
data present on the Pn inputs into the flip-flops, which makes it possible to use
the circuits as programmable counters. A Count Enable (CE) input serves as
the carry / borrow input in multi-stage counters. An Up / Down Count Control
(U/D) input determines whether a circuit counts up or down. A Terminal Count
(TC) output and a Ripple Clock (RC) output provide overflow/underflow
indication and make possible a variety of methods for generating
carry / borrow signals in multistage counter applications.
SN54/74LS190
SN54/74LS191
PRESETTABLE BCD / DECADE
UP/ DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
•
•
•
•
•
•
•
•
Low Power . . . 90 mW Typical Dissipation
High Speed . . . 25 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Parallel Load
Individual Preset Inputs
Count Enable and Up / Down Control Inputs
Cascadable
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
P0
15
CP
14
RC
13
TC
12
PL
11
P2
10
P3
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
P1
2
Q1
3
Q0
4
CE
5
U/D
6
Q2
7
Q3
8
GND
LOGIC SYMBOL
11 15
LOADING
(Note a)
HIGH
LOW
0.7 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5
4
14
U/D
CE
CP
Q0 Q1 Q2 Q3
3
2
6
7
TC
12
PL P0 P1 P2 P3
RC
13
1 10
9
PIN NAMES
CE
CP
U/D
PL
Pn
Qn
RC
TC
Count Enable (Active LOW) Input
Clock Pulse (Active HIGH going edge) Input
Up/Down Count Control Input
Parallel Load Control (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Ripple Clock Output (Note b)
Terminal Count Output (Note b)
1.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1
SN54/74LS190
•
SN54/74LS191
FUNCTIONAL DESCRIPTION
The LS190 is a synchronous Up / Down BCD Decade
Counter and the LS191 is a synchronous Up / Down 4-Bit
Binary Counter. The operating modes of the LS190 decade
counter and the LS191 binary counter are identical, with the
only difference being the count sequences as noted in the
state diagrams. Each circuit contains four master / slave
flip-flops, with internal gating and steering logic to provide
individual preset, count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information present
on the Parallel Data inputs (P0 – P3) is loaded into the counter
and appears on the Q outputs. This operation overrides the
counting functions, as indicated in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When CE is
LOW, internal state change are initiated synchronously by the
LOW-to-HIGH transition of the clock input. The direction of
counting is determined by the U/D input signal, as indicated in
the Mode Select Table. When counting is to be enabled, the
CE signal can be made LOW when the clock is in either state.
However, when counting is to be inhibited, the LOW-to-HIGH
CE transition must occur only while the clock is HIGH.
Similarly, the U / D signal should only be changed when either
CE or the clock is HIGH.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-down
mode or reaches maximum (9 for the LS190, 15 for the LS191)
in the count-up mode. The TC output will then remain HIGH
until a state change occurs, whether by counting or presetting
or until U / D is changed. The TC output should not be used as
a clock signal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When CE
is LOW and TC is HIGH, the RC output will go LOW when the
clock next goes LOW and will stay LOW until the clock goes
HIGH again. This feature simplifies the design of multi-stage
counters, as indicated in Figures a and b. In Figure a, each RC
output is used as the clock input for the next higher stage. This
configuration is particularly advantageous when the clock
source has a limited drive capability, since it drives only the
first stage. To prevent counting in all stages it is only necessary
to inhibit the first stage, since a HIGH signal on CE inhibits the
RC output pulse, as indicated in the RC Truth Table. A
disadvantage of this configuration, in some applications, is the
timing skew between state changes in the first and last stages.
This represents the cumulative delay of the clock as it ripples
through the preceding stages.
A method of causing state changes to occur simultaneously
in all stages is shown in Figure b. All clock inputs are driven in
parallel and the RC outputs propagate the carry / borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the
negative-going edge of the carry / borrow signal to ripple
through to the last stop before the clock goes HIGH. There is
no such restriction on the HIGH state duration of the clock,
since the RC output of any package goes HIGH shortly after its
CP input goes HIGH.
The configuration shown in Figure c avoids ripple delays
and their associated restrictions. The CE input signal for a
given stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The simple
inhibit scheme of Figures a and b doesn’t apply, because the
TC output of a given stage is not affected by its own CE.
MODE SELECT TABLE
INPUTS
MODE
PL
H
H
L
H
CE
L
L
X
H
U/D
L
H
X
X
CP
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
CE
L
H
X
RC TRUTH TABLE
INPUTS
TC*
H
X
L
CP
X
X
RC
OUTPUT
X
X
H
H
* TC is generated internally
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
= LOW Pulse
FAST AND LS TTL DATA
5-4
嵌入式系统
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