74LVC1G38-Q100
2-input NAND gate; open drain
Rev. 1 — 27 November 2013
Product data sheet
1. General description
The 74LVC1G38-Q100 provides a 2-input NAND function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Open drain outputs
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC1G38-Q100
2-input NAND gate; open drain
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC1G38GW-Q100
74LVC1G38GV-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP5
SC-74A
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic surface-mounted package; 5 leads
Version
SOT353-1
SOT753
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
YB
YB
Type number
74LVC1G38GW-Q100
74LVC1G38GV-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
2
A
Y 4
B
001aab717
1
2
&
4
001aab716
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration for SOT353-1 and SOT753
74LVC1G38_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 November 2013
2 of 13
NXP Semiconductors
74LVC1G38-Q100
2-input NAND gate; open drain
6.2 Pin description
Table 3.
Symbol
A
B
GND
Y
V
CC
Pin description
Pin
1
2
3
4
5
Description
data input
data input
ground (0 V)
data output
supply voltage
7. Functional description
Table 4.
Input
A
L
L
H
H
[1]
Function table
[1]
Output
B
L
H
L
H
Y
Z
Z
Z
L
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
+6.5
+6.5
50
100
-
+150
300
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
74LVC1G38_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 November 2013
3 of 13
NXP Semiconductors
74LVC1G38-Q100
2-input NAND gate; open drain
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
Active mode
Disable mode; V
CC
= 1.65 V to 5.5 V
Power-down mode; V
CC
= 0 V
T
amb
t/V
ambient temperature
input transition rise and V
CC
= 1.65 V to 2.7 V
fall rate
V
CC
= 2.7 V to 5.5 V
Conditions
Min
1.65
0
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
-
Max
5.5
5.5
5.5
5.5
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
[1]
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
I
CC
I
CC
C
I
input leakage current
OFF-state output current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A
V
I
= V
CC
0.6 V; I
O
= 0 A;
V
CC
= 2.3 V to 5.5 V; per pin
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
All information provided in this document is subject to legal disclaimers.
Conditions
Min
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.1
5
2.5
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
-
0.1
0.45
0.3
0.4
0.55
0.55
5
10
10
10
500
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
pF
power-off leakage current V
I
or V
O
= 5.5 V; V
CC
= 0 V
supply current
additional supply current
input capacitance
74LVC1G38_Q100
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 November 2013
4 of 13
NXP Semiconductors
74LVC1G38-Q100
2-input NAND gate; open drain
Table 7.
Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +125
C
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
I
CC
I
CC
input leakage current
OFF-state output current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A
V
I
= V
CC
0.6 V; I
O
= 0 A;
V
CC
= 2.3 V to 5.5 V; per pin
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
-
0.1
0.70
0.45
0.60
0.80
0.80
100
200
200
200
5000
V
V
V
V
V
V
A
A
A
A
A
V
V
V
V
V
V
V
V
Conditions
Min
Typ
Max
Unit
power-off leakage current V
I
or V
O
= 5.5 V; V
CC
= 0 V
supply current
additional supply current
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 6.
Symbol Parameter
t
pd
propagation delay
Conditions
A, B to Y; see
Figure 5
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
[2]
40 C
to +85
C
Min
1.0
0.5
0.5
0.5
0.5
Typ
[1]
3.0
1.8
2.5
2.3
1.5
Max
10.0
6.0
5.0
4.5
3.9
40 C
to +125
C
Min
1.0
0.5
0.5
0.5
0.5
Max
12.5
7.5
6.5
5.7
4.9
Unit
ns
ns
ns
ns
ns
74LVC1G38_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 November 2013
5 of 13
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