Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state; inverting
FEATURES
•
Inverting data path
•
3-state outputs interface directly with system bus
•
Output capability: bus driver
•
I
CC
category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT258 are high-speed Si-gate CMOS devices
and are pin compatible with Low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT258 have four identical 2-input multiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
1Y
=
OE
× (
1I
1
×
S
+
1I
0
×
S
)
2Y
=
OE
× (
2I
1
×
S
+
2I
0
×
S
)
3Y
=
OE
× (
3I
1
×
S
+
3I
0
×
S
)
4Y
=
OE
× (
4I
1
×
S
+
4I
0
×
S
)
74HC/HCT258
Data appears at the outputs (1Y to 4Y) in inverted form
from the select inputs.
The ‘258’ is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determined by
the logic levels applied to S. The outputs are forced to a
high impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
The ‘258’ is identical to the ‘257’ but has inverting outputs.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
nI
0
, nI
1
to nY
S to nY
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. For HC the condition is V
I
= GND to V
CC
;
For HCT the condition is V
I
= GND to V
CC
−
1.5 V.
input capacitance
power dissipation capacitance per multiplexer
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
9
14
3.5
55
13
16
3.5
38
HCT
ns
ns
pF
pF
UNIT
1999 Sep 02
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state; inverting
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
74HC258N;
74HCT258N
74HC258D;
74HCT258D
74HC258DB
PIN DESCRIPTION
PIN NO.
1
2, 5, 11 and 14
3, 6, 10 and 13
4, 7, 9 and 12
8
15
16
SYMBOL
S
1I
0
to 4I
0
1I
1
to 4I
1
1Y to 4Y
GND
OE
V
CC
common data select input
data inputs from source 0
data inputs from source 1
3-state multiplexer outputs
ground (0 V)
3-state output enable input (active LOW)
positive supply voltage
NAME AND FUNCTION
DIP16
SO16
SSOP16
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
74HC/HCT258
VERSION
SOT38-1
SOT109-1
SOT338-1
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 5.3 mm
fpage
fpage
fpage
1
15
1
2
3
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
OE
MGA832
G1
EN
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
16
VCC
15
OE
14
3I0
S
1Y
4
2
2Y
7
3
5
3Y
9
6
11
4Y
12
10
14
13
5
6
14
13
11
1
1
MUX
4
258
5
6
7
8
MGA830
13
3I1
12
4Y
11
4I0
10
4I1
9
3Y
7
9
10
15
12
MGA831
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1999 Sep 02
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state; inverting
74HC/HCT258
handbook, full pagewidth
2
1I0
3
1I1
5
2I0
6
2I1
14
3I0
13
3I1
11
4I0
10
4I1
1
S
SELECTOR
15
OE
3-STATE MULTIPLEXER OUTPUTS
1Y
4
2Y
7
3Y
12
4Y
9
MBL095
Fig.4 Functional diagram.
FUNCTION TABLE
See note 1
INPUTS
OE
H
L
L
L
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
3I0
3Y
3I1
OUTPUT
nI
1
X
L
H
X
X
Z
H
L
H
L
nY
1I0
1Y
1I1
S
X
H
H
L
L
X
X
X
L
H
nI
0
2I0
2Y
2I1
4I0
4Y
4I1
OE
S
MBL096
Fig.5 Logic diagram.
1999 Sep 02
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state; inverting
DC CHARACTERISTICS FOR 74HC
74HC/HCT258
For the DC characteristics see chapter
“HCMOS family characteristics”,
section “Family specifications”.
Output capability: bus driver.
I
CC
category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
T
amb
(°C)
SYMBOL
PARAMETER
MIN.
t
PHL
/t
PLH
propagation delay;
nI
0
to nY; nI
1
to nY
propagation delay;
S to nY
−
−
−
−
−
−
t
PZH
/t
PZL
3-state output
enable time
OE to nY
3-state output
disable time
OE to nY
output transition
time
−
−
−
−
−
−
−
−
−
25
TYP.
30
11
9
47
17
14
39
14
11
55
20
16
14
5
4
MAX.
95
19
16
140
28
24
140
28
24
150
30
26
60
12
10
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−40
to +85
MIN.
MAX.
120
24
20
175
35
30
175
35
30
190
38
33
75
15
13
−40
to +125
MIN.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TEST CONDITIONS
UNIT V
CC
WAVEFORMS
(V)
MAX.
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
ns
2.0
4.5
6.0
see Fig.6
see Fig.7
see Fig.7
see Fig.6
see Fig.6
145
29
25
210
42
36
210
42
36
225
45
38
90
18
15
t
PHZ
/t
PLZ
t
THL
/t
TLH
1999 Sep 02
5
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