74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 19 May 2014
Product data sheet
1. General description
The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops
with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is
stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and
outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are
required and the clock and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC175-Q100: CMOS level
For 74HCT175-Q100: TTL level
Four edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC175D-Q100
74HCT175D-Q100
74HC175PW-Q100
74HCT175PW-Q100
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width SOT109-1
3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Type number
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74HC_HCT175_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
2 of 18
NXP Semiconductors
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration SO16
Fig 5.
Pin configuration TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
Q0 to Q3
Q0 to Q3
D0 to D3
GND
CP
V
CC
Pin description
Pin
1
2, 7, 10, 15
3, 6, 11, 14
4, 5, 12, 13
8
9
16
Description
asynchronous master reset input (active LOW)
flip-flop output
complementary flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
74HC_HCT175_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
3 of 18
NXP Semiconductors
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
reset (clear)
load “1”
load “0”
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Outputs
CP
X
Dn
X
h
l
Qn
L
H
L
Qn
H
L
H
L
H
H
Fig 6.
Functional diagram
74HC_HCT175_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
4 of 18
NXP Semiconductors
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[1]
-
For SO16 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC175-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT175-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT175_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
5 of 18
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