CoreDES
Product Summary
Intended Use
•
•
Whenever Data is Transmitted across an Accessible
Medium (Wires, Wireless, etc.)
E-Commerce Transactions, where Dedicated
Encryption/Decryption Hardware Can Ease the
Load on Servers
Personal Security Devices
Bank Transactions, where Financial Security is
Mandatory
•
•
Core Deliverables
•
Evaluation Version
–
Compiled RTL Simulation Model Fully
Supported in the Actel Libero
®
Integrated
Design Environment (IDE)
Structural Verilog and VHDL Netlists (with and
without I/O pads) Compatible with the Actel
Designer Place-and-Route Software Tool
Compiled RTL Simulation Model
Supported in the Actel Libero IDE
Verilog or VHDL Core Source Code
Core Synthesis Scripts
Fully
Netlist Version
–
•
•
–
RTL Version
–
–
Key Features
•
•
•
•
•
•
•
•
•
•
56-bit Cipher Key (with 8 Additional Parity Bits)
Parity Checking Logic for Cipher Key
Encryption and Decryption Possible with Same
Core
16-Clock Cycle Operation to Encrypt or Decrypt 64
Bits of Data
Pause/Resume
Functionality
Encryption or Decryption at Will
Compliant with FIPS PUB 46-3
ECB (Electronic Codebook) Implementation per
FIPS PUB 81
Example Source Code Provided for CBC, CFB and
OFB Modes
Provides Data Security within a Secure Actel FPGA
All Major Actel Device Families Supported
•
to
Continue
•
Actel-Developed Testbench (Verilog and VHDL)
Synthesis and Simulation Support
•
Synthesis:
Synplicity
®
,
Synopsys
®
(Design
®
Compiler / FPGA Compiler
™
/ FPGA Express
™
),
Exemplar
™
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
•
Core Verification
•
Actel-Developed Simulation Testbench Verifies
CoreDES against Tests Listed in the National
Institute of Standards and Technology (NIST)
Special Publication 800-17,
Modes of Operation
Validation System (MOVS): Requirements and
Procedures
Users Can Easily Modify Testbench Using Existing
Format to Add More Tests Listed in NIST Special
Publication 800-17 or Custom Tests
Supported Families
•
•
•
•
•
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•
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
December 2005
© 2005 Actel Corporation
v 4 .0
1
CoreDES
Contents
General Description .................................................... 2
CoreDES Device Requirements .................................. 4
CoreDES Verification .................................................. 4
I/O Signal Descriptions ............................................... 5
CoreDES Operation .................................................... 5
Encryption ................................................................... 6
Decryption .................................................................. 7
Pause/Resume ............................................................. 8
Clear/Abort ................................................................. 9
Modes of Operation ................................................... 9
Ordering Information .............................................. 10
Export Restrictions .................................................... 10
List of Changes ......................................................... 11
Datasheet Categories ............................................... 11
General Description
The CoreDES macro implements the Data Encryption
Standard (DES), which provides a means of securing data.
The DES algorithm is described in
Federal Information
Processing Standards (FIPS) Publication (PUB) 46-3.
The
algorithm takes as input 64 bits of plaintext data and 64
bits of a cipher key (only 56 of the 64 bits of the key are
used in the calculations, as the least significant bit of
each byte of the cipher key is used to provide odd-parity
for the key bytes) and after 16 cycles, produces a 64-bit
ciphered version of the original plaintext data as output.
During the 16 cycles or iterations of the algorithm, the
data bits are subjected to permutation and addition
functions, which consist of key schedules, calculated by
rotations and permutations applied to the original 56-bit
cipher key.
Figure 1
illustrates the 16-iteration DES
algorithm, as described in detail in
FIPS PUB 46-3.
L0
R0
Left and Right
Data Halves after
Initial Permutation
K1
Key Schedule 1
+
f
Key
Input
Initial
Permutation
L1 = R0
R1 = L0
f(R0,K1)
K2
Left and Right
Data Halves after
Round 1
Key Schedule 2
16 Rounds
of Computation
+
Inverse Initial
Permutation
Output
L2 = R1
R2 = L1
f(R1,K2)
f
Left and Right
Data Halves
after Round 2
R16 = L15
f(R15,K16)
L16 = R15
Left and Right
Data Halves
after Round 16
Figure 1 •
DES Algorithm
2
v4.0
CoreDES
CoreDES consists of four main blocks (shown in
Figure 2).
1. Data schedule logic – computes the intermediate
data values at each round of the DES algorithm.
2. Iteration state machine logic – keeps track of
which round of the DES algorithm is currently in
progress.
3. Key schedule logic – computes the intermediate
keys at each round of the DES algorithm.
4. Parity check logic – checks for odd-parity
compliance of the 56 bits of cipher key and issues
an error signal if parity is not correct.
Data In
Data
schedule
logic
Iteration
state
machine
Data Out
Cipher Key
Key
schedule
logic
Parity
check
logic
Parity Error
Parity Enable
Figure 2 •
CoreDes Block Diagram
Design Security
Figure 3
shows a typical system diagram. Note
that the cipher key, which is the "secret" key, can be
made up of FPGA logic cells thereby preventing the
possibility of design or data theft. Actel Flash-based
devices (ProASIC
PLUS
) employ FlashLock
TM
technology,
and Actel antifuse-based devices (Axcelerator, SX-A,
Actel FPGA
RT54SX-S) employ FuseLock
TM
technology, each of which
provides a means to keep the cipher key and the rest of
the logic secure. The output of the CoreDES macro
should be connected to registers or FIFOs, as it is only
valid for one clock cycle, as shown in the
sections"Encryption"
on page 6
and
"Decryption" on
page 7,
respectively.
Local Device
Plaintext
(Unencrypted)
Data
Source
Registers or
FIFO
Other
Logic
CoreDES
Other
Logic
To other logic or
global distribution,
e.g., Internet, etc.
Encrypted
Data
Output
Cipher
Key
Figure 3 •
CoreDES in Typical System
v4.0
3
CoreDES
CoreDES Device Requirements
The CoreDES macro has been implemented in several of the Actel device families. A summary of the implementation
data is listed in
Table 1.
Table 1 •
CoreDes Device Utilization and Performance
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
Note:
Sequential
148
148
142
141
141
141
141
Combinatorial
1123
1123
1328
601
601
628
628
Total
1271
1271
1470
742
742
769
769
Utilization
Device
AFS600
A3PE600-2
APA075-STD
AX125-3
RTAX1000S-1
A54SX16A-3
RT54SX32S-2
Total
10%
10%
48%
37%
4%
53%
27%
Performance
80 MHz
80 MHz
50 MHz
125 MHz
74 MHz
100 MHz
55 MHz
Throughput
320 Mbps
320 Mbps
200 Mbps
500 Mbps
296 Mbps
400 Mbps
220 Mbps
Data in this table achieved using typical synthesis and layout settings.
Data throughput is computed by taking the bit width of the data (64 bits), dividing by the number of cycles (16), and
multiplying by the clock rate (performance); the result is listed in Mbps (millions of bits per second).
CoreDES Verification
The comprehensive simulation testbench (included with
Netlist and RTL versions of the core) verifies the CoreDES
macro against several of the tests listed in NIST Special
Publication 800-17,
Modes of Operation Validation
System (MOVS): Requirements and Procedures.
The
testbench applies several tests to the CoreDES macro,
including: sample round output tests, variable plaintext
tests, variable cipher key tests, permutation operation
tests, and substitution table tests. Using the supplied
testbench as a guide, the user can easily customize the
verification of the core by adding or removing any of the
tests listed in
NIST Special Publication 800-17
or by
adding any custom test cases.
4
v4.0
CoreDES
I/O Signal Descriptions
The port signals for the CoreDES macro are defined in
Table 2
and illustrated in
Figure 4.
CoreDES has 200 I/O
signals that are described in
Table 2.
All arrayed ports are
labeled with indices that begin with the number 1 (most
significant bit) and ascend up to the width of the arrayed
Table 2 •
CoreDES I/O Signal Descriptions
Name
NRESET
CLK
EN
CLR
ED
PCHK
K[1:64]
D[1:64]
Q[1:64]
QVAL
PERR
Type
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Description
Active-low asynchronous reset
System clock: reference clock for all internal DES logic
Enable signal: set to '1' for normal continuous operation, set to '0' to pause
Synchronous clear signal: set to '1' to clear logic at any time
Encrypt/Decrypt: '1' to Encrypt, '0' to Decrypt
Parity Check: set to '1' to enable parity checking of cipher key bits
Key: 64-bit (56 bits + 8 parity bits) cipher key input bus
Data in: 64-bit data input bus
Data out: 64-bit ciphertext (for Encrypt operation, plaintext for Decrypt operation)
Q Valid: '1' indicates that valid Encrypt/Decrypt data is available on Q
Parity Error: '1' indicates that a parity error has occurred on the K cipher key input bits
port (least significant bit, which happens to be 64 for all
arrayed ports in this core). The arrayed ports are labeled
in this fashion to correspond with the nomenclature
described in
Federal Information Processing Standards
Publication 46-3 (FIPS PUB 46-3).
CoreDES Operation
NRESET
CLK
EN
CLR
ED
PCHK
K[1:64]
D[1:64]
Figure 4 •
CoreDES I/O Signal Diagram
Parity Checking
CoreDES
Q[1:64]
QVAL
PERR
If parity checking is desired for the cipher key K[1:64]
inputs, the PCHK input should be held at logic '1'. The
parity checking logic will determine whether or not an
odd number of logic '1' values are present in each byte
of the cipher key. This function can be disabled at any
time by setting the PCHK input to logic '0'.
Note that if parity checking is disabled by setting the
PCHK input to logic '0,' the least significant bits of each
byte of the cipher key (K[8], K[16], K[24], K[32], K[40],
K[48], K[56], and K[64]) can each be statically connected
to either a logic '1' or logic '0' value, since they are the
parity bits and will not be used (Figure
5).
K[1:64]
32
8
16
24
40
48
56
64
PCHK
Figure 5 •
Key Parity Check
Parity Check
Logic
PERR
v4.0
5
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