74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 02 — 19 March 2008
Product data sheet
1. General description
The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on
the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the
clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101-C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP2G79DC
74AUP2G79GT
74AUP2G79GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
VSSOP8
XSON8
XQFN8U
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT902-1
Type number
4. Marking
Table 2.
Marking codes
Marking code
p79
p79
p79
Type number
74AUP2G79DC
74AUP2G79GT
74AUP2G79GM
5. Functional diagram
1D
1Q
1CP
2D
2Q
2CP
001aah811
D
CP
D
CP
001aah812
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
mna442
Fig 3.
74AUP2G79_2
Logic diagram (one flip-flop)
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 19 March 2008
2 of 19
NXP Semiconductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
6. Pinning information
6.1 Pinning
74AUP2G79
1CP
1D
2Q
GND
1
2
3
4
001aaf268
8
7
6
5
V
CC
1Q
2D
2CP
Fig 4.
Pin configuration SOT765-1 (VSSOP8)
74AUP2G79
74AUP2G79
1CP
1
8
V
CC
terminal 1
index area
1Q
1
V
CC
8
7
1CP
1D
2
7
1Q
2D
2
6
1D
2Q
3
6
2D
2CP
3
4
5
2Q
GND
GND
4
5
2CP
001aaf270
001aaf269
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT833-1 (XSON8)
Fig 6.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
1CP
1D
2Q
GND
2CP
2D
1Q
V
CC
Pin description
Pin
SOT765-1 and SOT833-1
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
clock pulse input 1
data input 1
data output 2
ground (0 V)
clock pulse input 2
data input 2
data output 1
supply voltage
Description
74AUP2G79_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 19 March 2008
3 of 19
NXP Semiconductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
7. Functional description
Table 4.
Input
nCP
↑
↑
L
[1]
Function table
[1]
Output
nD
L
H
X
nQ
L
H
q
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
-
−0.5
-
[1]
Max
+4.6
−50
+4.6
±50
+4.6
±20
50
−50
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
-
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP2G79_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 19 March 2008
4 of 19
NXP Semiconductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
µA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OFF
∆I
OFF
I
CC
∆I
CC
C
I
C
O
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
additional supply current
input capacitance
output capacitance
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
per pin; V
I
= V
CC
−
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
V
CC
= 0 V to 3.6 V; V
I
= GND or V
CC
V
O
= GND; V
CC
= 0 V
[1]
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.6
1.3
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
0.5
40
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
pF
pF
0.75
×
V
CC
-
74AUP2G79_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 19 March 2008
5 of 19
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