74AUP1T98-Q100
Low-power configurable gate with voltage-level translator
Rev. 1 — 19 May 2014
Product data sheet
1. General description
The 74AUP1T98-Q100 provides low-power, low-voltage configurable logic gate functions.
Eight patterns of 3-bit input determine the output state. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T98-Q100 is designed for logic-level translation applications. The input
switching levels accept 1.8 V low-voltage CMOS signals, while operating from either a
single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Low static power consumption; I
CC
= 1.5
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
NXP Semiconductors
74AUP1T98-Q100
Low-power configurable gate with voltage-level translator
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
H
H
L
L
H
L
H
L
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 3
see
Figure 4
see
Figure 5
see
Figure 5
see
Figure 6
see
Figure 6
see
Figure 7
see
Figure 8
see
Figure 9
Logic function
2-input MUX (inverting)
2-input NAND
2-input NOR with one input inverted
2-input AND with one input inverted
2-input NAND with one input inverted
2-input OR with one input inverted
2-input NOR
Buffer
Inverter
74AUP1T98-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
3 of 16
NXP Semiconductors
74AUP1T98-Q100
Low-power configurable gate with voltage-level translator
Fig 3.
2-input MUX (inverting)
Fig 4.
2-input NAND gate
Fig 5.
2-input AND gate with input A inverted or
2-input NOR gate with input C inverted
Fig 6.
2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
Fig 7.
2-input NOR gate
Fig 8.
Buffer
Fig 9.
Inverter
74AUP1T98-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
4 of 16
NXP Semiconductors
74AUP1T98-Q100
Low-power configurable gate with voltage-level translator
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 package: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
2.3
0
0
0
40
Max
3.6
3.6
V
CC
3.6
+125
Unit
V
V
V
V
C
74AUP1T98-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
5 of 16
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