DATA SHEET
SKY74038: 2.6 GHz/800 MHz Dual Fractional-N/lnteger-N
Frequency Synthesizer
Applications
•
Multi-slot GSM/DCS
•
PCS/W-CDMA
•
Portable communication systems
•
Dual-mode cellular telephone systems
•
Spread spectrum receivers
•
Wireless LAN systems
•
Wireless routers and WLL systems
•
SATCOM receivers
Description
Skyworks SKY74038 is a complete, low-power 2.6 GHz/800 MHz
dual frequency synthesizer. The device provides both Radio
Frequency (RF) channels and Intermediate Frequency (IF)
channels. Fractional-N operation offers low phase noise, fast
settling time, and low spurious tones for RF channels. A standard
integer-N division is used for IF channels.
The three-wire serial interface provides programmable control of
the frequency synthesizer to support dual-conversion
transceivers.
The SKY74038 is available as a 20-pin Thin Shrink Small Outline
Package (TSSOP) (-13 option) or as a Pb-free 20-pin TSSOP (-21
option). The device package and pin configuration are shown in
Figure 1. A functional block diagram of the SKY74038 is shown in
Figure 2.
Features
•
Maximum operating frequency: 2.6 GHz
•
Maximum IF synthesizer frequency: 800 MHz
•
Supply voltage as low as 2.6 V
•
Fast frequency settling time with fractional-N operation
•
Internal fractional spur reduction
•
Programmable charge pump currents
•
Digital lock detector
•
Power saving at lower frequency
•
Two package options, both 20-pin, 6.5 x 4.4 x 1.0 mm TSSOPs:
−
SKY74038-13 (MSL3, 225
°C
per JEDEC J-STD-020)
−
SKY74038-21, Pb-free (MSL3, 260
°C
per JEDEC J-STD-
020)
Skyworks offers lead (Pb)-free, RoHS (Restriction of
Hazardous Substances) compliant packaging.
VDD1_RF
VDD2_RF
CPO_RF
GND
RFIN
RFINB
GND
FREF
GND
LD_TP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD1_IF
VDD2_IF
CPO_IF
GND
IFIN
IFINB
GND
LE
DAT
CLK
C1452
Figure 1. SKY74038 Pinout – 20-Pin TSSOP
(Top View)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101075M • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • June 4, 2007
1
DATA SHEET • SKY74038 FREQUENCY SYNTHESIZER
GND
VDD2_RF
VDD1_RF
GND
CPO_RF
GND
R1
SP1
SC1
FREF
R1
Divider
P/FD 1
Charge
Pump 1
N1
PS
N1
Divider
P/P+1
Prescaler
RFIN
RFINB
LD_TP
MUX
(LD/TEST)
FN
ME
∆Σ
Modulator
Q/Q+1
Prescaler
IFIN
IFINB
LE
CLK
DAT
LD
N2
Divider
N2
R2
Divider
P/FD 2
Charge
Pump 2
Serial-to Parallel
Interface
R2
SP2
SC2
C1451
VDD2_IF
VDD1_IF
GND
CPO_IF
GND
Figure 2. SKY74038 Block Diagram
Technical Description
The SKY74038 is a fractional-N frequency synthesizer using a
∆Σ
modulation technique. The fractional-N implementation provides
low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the SKY74038 provides
arbitrarily fine frequency resolution with digital words, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
∆Σ
Modulator
Fractional spurs are the primary limitation of conventional
fractional-N synthesizers. The SKY74038
∆Σ
technique improves
the synthesizer performance by randomizing the spurs using
internal dithering.
Serial Interface
The serial interface is a versatile three-wire interface consisting of
three pins: the serial clock (CLK), serial input (DAT), and Latch
Enable (LE). This interface enables the SKY74038 to operate in a
system where one or multiple masters and slaves are present. For
more information, refer to the Synthesizer Register Programming
section of this document.
As shown in Figure 3, LE is set low before the rising edge of the
first clock (CLK) pulse and is held low until after the last (22
nd
)
clock pulse, at which time LE is set high. The data word is
transferred to the correct device register when LE is high (there
are four internal registers selected by the D1 and D0 bits of the
22-bit data/address word. See Figure 4). If the LE signal does not
go high, the data does not get transferred to the register.
Between each 22-bit data/address word transfer, LE must be
pulsed to make the transfer to the specific device register.
Data/address transfer is MSB first.
LE must not go high when CLK is high; otherwise, the data word
is not transferred to the register. LE must only go high after CLK
has gone low.
After the transfer of the last 22-bit data/address word, the LE
signal can be left in a high state. It does not have to be returned
to a low state unless another data/address word transfer is
required.
It is not necessary to write all four data/address words to the
synthesizer to make a change in programming. For example, if a
change to the Lock Detect (LD) pin operation is desired, only word
00 has to be changed.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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June 4, 2007 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101075M
DATA SHEET • SKY74038 FREQUENCY SYNTHESIZER
DAT
CLK
LE
t
DSU
t
DHD
t
CKH
t
CKL
t
CLE
t
LEW
C1457
t
LEC
Figure 3. SKY74038 Serial Data Input Timing Diagram (MSB First)
MSB
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
LD
EN
R1 DIVIDER
FN
PS
SC1
D4
D3
SC2
SP2
SP1
D2
D1
0
1
0
1
LSB
D0
0
IF
N2 DIVIDER
ME
N1 DIVIDER
0
1
RF
1
C1456
R2 DIVIDER
Figure 4. SKY74038 Serial Data Word Format
Registers
The SKY74038 includes four 22-bit registers that can be
programmed independently in any order. Bits D0 and D1
represent the register addresses. For more information on
registers, addresses, and format, refer to the Synthesizer Register
Programming section of this document.
A dithering disable function is accessible via word 00, data bits
21 and 20. When the RF synthesizer is programmed for fractional
divide values, bits [21:20] should be programmed to 10b to
enable dithering. However, when the RF synthesizer is
programmed to output a frequency that is a whole integer
multiple of the comparison frequency, the synthesizer should be
programmed to disable dithering (bits [21:20] = 11b). This
improves the phase noise when operating on integer-N
boundaries. These data bits must be programmed after power-up;
otherwise, erroneous device operation may occur. Refer to the
Synthesizer Register Programming section of this document for
bit definitions.
Voltage Controlled Oscillator (VCO) Prescalers
The VCO prescalers, P/P+1 and Q/Q+1, provide low noise signal
conditioning of the VCO signals. They translate from an off-chip,
single-ended or differential signal to an on-chip differential signal.
By changing the PS bit, the RF synthesizer has the option to use
either the 8/9 or the 16/17 prescaler depending on the desired
operational frequency. The maximum frequency is 2.6 GHz for the
16/17 prescaler and 1.4 GHz for the 8/9 prescaler. The IF
synthesizer has a fixed 16/17 prescaler with a maximum
frequency of 800 MHz.
RF and IF Dividers
The SKY74038 provides programmable dividers that control the
prescaler and supply the divided VCO signals to the charge pump
phase detectors. Programmable ratios on the RF fractional-N
synthesizer ranging from 256 to 2
12
are possible with the 16/17
prescaler, and from 64 to 2
11
with the 8/9 prescaler. The IF
integer-N synthesizer has a programmable divide ratio ranging
from 256 to 2
17
.
Reference Frequency Dividers
The reference signal can be divided by a ratio of 1 to 7 for the RF
reference divider (R1) and from 1 to 8192 for the IF reference
divider (R2). The input frequency for the reference signal can be
as high as 50 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101075M • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • June 4, 2007
3
DATA SHEET • SKY74038 FREQUENCY SYNTHESIZER
Phase Detectors and Charge Pumps
The SKY74038 uses a separate charge pump phase detector for
each synthesizer. The IF and RF Phase/Frequency Detector (PFD)
can have a programmable charge pump current from 0.4 mA to
1.6 mA and 120
µA
to 480
µA,
respectively.
For optimum performance, the divided reference frequency
presented at the phase detector input must not exceed 9 MHz
using the RF 16/17 prescaler synthesizer mode, 15 MHz using the
RF 8/9 prescaler, or 2 MHz for the IF synthesizer mode. The
comparison frequency is also limited by the desired frequency
divided by the minimum divide ratio.
The charge pump can be programmed to a high impedance (Hi-Z)
state for open-loop VCO modulation use.
The fractional modulo can be extended up to 2
21
using the modulo
extender (ME), if required, as shown by the following equation:
⎛
1
ME
=
D
21
⎜
9
⎜
⎝
2
⎞
⎛
1
⎟ +
D
20
⎜
⎟
⎜
10
⎠
⎝
2
⎞
⎟
⎟
⎠
⎛
1
+
D19
⎜
11
⎜
⎝
2
⎞
⎛
1
⎟ +
...
+
D
9
⎜
⎟
⎜
21
⎠
⎝
2
⎞
⎟
⎟
⎠
Because of the way the
∆Σ
modulator is implemented in the
SKY74038, the number 3.5 must be added to the division number
to obtain the final division ratio. If the integer field of the N divider
shows a non-integer number, the desired frequency or the
division fraction portion needs to be adjusted.
Sample calculations for two fractional-N applications are shown
in Figure 5.
Package and Handling Information
Lock Detection
The output of the IF/RF dividers (R1, N1, R2, N2) and lock
detectors for both synthesizers can be multiplexed to the LD pin.
When programmed for lock detection, the SKY74038 provides an
active low output to indicate the out-of-lock condition. When
locked, the LD pin is high.
Power Down
The SKY74038 supports a number of power-down modes through
the serial interface. Both IF and RF synthesizer blocks can be
powered down, powered up individually, or both powered up
using the EN bits (see the Synthesizer Register Programming
section of this document). The SKY74038 is enabled at power up
by default.
Synthesizer Register Programming
IF Integer-N Synthesizer.
The N2 17-bit divider ratio is
calculated using the following equation:
F
REF
-
IF
=
N2
×
------------
R2
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
The following two product options are available for the SKY74038:
•
The SKY74038-13 is rated to Moisture Sensitivity Level 3
(MSL3) at 225
°C.
It should only be used with lead solder.
•
The SKY74038-21 is rated to MSL3 at 260
°C
and can be used
with either lead or lead-free solder.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format. For packaging details, refer to the Skyworks
Application Note,
Tape and Reel,
document number 101568.
Electrical and Mechanical Specifications
Signal pin assignments and functional pin descriptions are
specified in Table 1. The absolute maximum ratings of the
SKY74038 are provided in Table 2. The recommended operating
conditions are specified in Table 3 and electrical characteristics
are provided in Table 4.
Table 5 provides the register descriptions. Package dimensions
for the SKY74038 are shown in Figure 6 and tape and reel
dimensions for the 20-pin TSSOP package are shown in Figure 7.
As with all integer-N synthesizers, the minimum step size is
related to the divided reference frequency,
F
REF
.
RF Fractional-N Synthesizer.
The N1 divider ratio is calculated
using the following equation:
F
REF
-
RF
= ------------
×
N1
Total
R1
where:
N1
Total
= N1 + 3.5 + FN + ME
Electrostatic Discharge Information
The SKY74038 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper ESD
precautions.
FN sets the fractional-N modulo up to 256 modulo, as calculated
by the following equation:
⎛
1
⎛
1
⎞
FN
=
D
9
⎜ ⎟ +
D
8
⎜
2
⎜
⎝
2
⎠
⎝
2
⎞
⎛
1
⎟ +
D
7
⎜
⎟
⎜
3
⎠
⎝
2
⎞
⎛
1
⎟ +
...
+
D
2
⎜
⎟
⎜
8
⎠
⎝
2
⎞
⎟
⎟
⎠
where
D
n
represents the bit locations within the register field.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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June 4, 2007 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101075M
DATA SHEET • SKY74038 FREQUENCY SYNTHESIZER
Case 1:
To achieve a desired F
VCO_RF
frequency of 2440.2 MHz using a crystal frequency of 24 MHz with operation
of the synthesizer in RF mode using the 16/17 prescaler (PS = 1). R1 is set to divide by 3 to achieve a
comparison frequency of 8 MHz, since the maximum internal reference frequency is 9 MHz. Divide the operating
frequency by the internal reference frequency to determine the value of N
Total
:
N
Total
= 2440.2 MHz
8 MHz
=
305.025
Subtract 3.5 from N
Total
and remove the fractional portion of the result to determine N1:
305.025 – 3.5 = 301.525
N1 = 301 (decimal)
Fractional portion = 0.525 (decimal)
N1 = 000100101101 (binary)
D
21
-----------D
10
Register Address 11
2
Multiply the fractional portion of N1 by 256 and remove the fractional portion of the result to determine FN:
0.525 × 256 = 134.4
FN = 134 (decimal)
FN = 10000110 (binary)
D
9
-------D
2
Register Address 11
2
Divide FN by 256 to determine the actual fractional portion:
134 = 0.5234375
256
Subtract this result from the fractional portion of N1:
0.525 – 0.5234375 = 0.0015625
Multiply this result by 2097152 (the 21-bit
∆Σ
modulator value 2
21
) and remove the fractional portion to determine
the ME:
0.0015625 × 2097152 = 3276.8
ME = 3276 (decimal)
ME = 0110011001100 (binary)
D
21
--------------D
9
Register Address 01
2
In this example, N1 is greater than 256, the minimum divide ratio for the 16/17 prescaler.
C1454
Figure 5. Fractional-N Applications: Sample Calculation (1 of 2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101075M • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • June 4, 2007
5
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