74AUP1T97
Low-power configurable gate with voltage-level translator
Rev. 5 — 17 September 2015
Product data sheet
1. General description
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
2. Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 1.5
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1T97
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1T97GW
74AUP1T97GM
74AUP1T97GF
74AUP1T97GN
74AUP1T97GS
74AUP1T97GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
Version
SOT363
SOT886
SOT891
SOT1115
SOT1202
Type number
X2SON6 plastic thermal extremely thin small outline package; SOT1255
no leads; 6 terminals; body 1
0.8
0.35 mm
4. Marking
Table 2.
Marking
Marking code
[1]
59
59
59
59
59
59
Type number
74AUP1T97GW
74AUP1T97GM
74AUP1T97GF
74AUP1T97GN
74AUP1T97GS
74AUP1T97GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 17 September 2015
2 of 22
NXP Semiconductors
74AUP1T97
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 5.
Pin configuration SOT1255 (X2SON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 17 September 2015
3 of 22
NXP Semiconductors
74AUP1T97
Low-power configurable gate with voltage-level translator
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
H
H
L
H
L
H
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 6
see
Figure 7
see
Figure 8
see
Figure 8
see
Figure 9
see
Figure 9
see
Figure 10
see
Figure 11
see
Figure 12
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
Fig 6.
2-input MUX
Fig 7.
2-input AND gate
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 17 September 2015
4 of 22
NXP Semiconductors
74AUP1T97
Low-power configurable gate with voltage-level translator
Fig 8.
2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig 9.
2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
Fig 10. 2-input OR gate
Fig 11. Inverter
Fig 12. Buffer
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 17 September 2015
5 of 22
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