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5962L102301QYC

产品描述Synchronous DRAM,
产品类别存储    存储   
文件大小1MB,共69页
制造商Cobham PLC
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5962L102301QYC概述

Synchronous DRAM,

5962L102301QYC规格参数

参数名称属性值
厂商名称Cobham PLC
包装说明,
Reach Compliance Codeunknown
内存集成电路类型SYNCHRONOUS DRAM
认证状态Not Qualified
总剂量50k Rad(Si) V
Base Number Matches1

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Standard Products
UT8SDMQ64M40 2.5-Gigabit SDRAM MCM
UT8SDMQ64M48 3.0-Gigabit SDRAM MCM
Datasheet
March 25, 2013
FEATURES
Organized as 64M x 40 (16Meg x 40 x 4 banks) and 64M
x 48 (16Meg x 48 x 4 banks)
Single 3.3V power supply
PC100-compliant
Operation -40
o
C to +105
o
C
LVTTL compatible with multiplexed address
Fully synchronous; all signals registered on positive edge
of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Programmable burst lengths: 1,2,4,8, or full page
Auto-precharge, includes concurrent auto precharge, and
auto-refresh mode
32ms, 8,192-cycle refresh
Operational environment:
- Total dose: 100 krad(Si)
- SEL Immune 111 MeV-cm
2
/mg
- SEU Event Rate: 1.3E-10 events/bit-day assuming
geosynchronous orbit and Adam’s 90% worst-case
environment
Package options:
- 128-lead Ceramic Quad Flatpack, shallow side-braze
- 128-lead Ceramic Quad Flatpack, deep side-braze
Standard Microcircuit Drawing
- UT8SDMQ64M40: 5962-10229
- UT8SDMQ64M48: 5962-10230
- QML Q and Q+
INTRODUCTION
The UT8SDMQ64M40 and UT8SDMQ64M48 are high
performance, highly integrated Synchronous Dynamic Random
Access Memory (SDRAM) multi-chip modules (MCMs). Total
module density is 2,684,354,560 bits for the 2.5G device and
3,221,225,472 bits for the 3G device. Each bit bank is organized
as 8192 rows by 2048 columns.
Read and write accesses to the DRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
The programmable READ and WRITE burst lengths (BL) are
1, 2, 4, or 8 locations, or the full page, with a burst terminate
option.
Aeroflex’s SDRAMs are designed to operate at 3.3V. An auto-
refresh mode is provided, along with a power-saving, power-
down mode. All inputs and outputs are LVTTL compatible.
SDRAMs offer significant advances in DRAM operating
execution, including the capability to synchronously burst data
at a high data rate with automatic column-address generation,
to interleave between internal banks to mask precharging time,
and to randomly change column addresses on each clock cycle
during a burst access.
40
DQM5
48
U5
U4
U3
U2
8
8
8
DQM4
DQM3
DQM2
DQM1
DQM0
A[12:0]
BA[1:0]
CLK
CKE
RAS#
CAS#
WE#
CS#
15
U4
U3
U2
U1
8
8
DQM4
8
DQ[7:0](5)
DQ[7:0](4)
DQ[7:0](3)
8
DQ[47:40]
DQ[39:32]
DQ[31:24]
DQ[23:16]
DQ[15:8]
DQ[7:0]
DQ[7:0](4)
DQ[7:0](3)
8
DQ[39:32]
DQ[31:24]
DQ[23:16]
DQ[15:8]
DQ[7:0]
DQM3
DQM2
DQM1
DQM0
A[12:0]
BA[1:0]
CLK
CKE
RAS#
CAS#
WE#
CS#
15
DQ[7:0](2)
DQ[7:0](1)
8
U1
U0
SDRAM
16Meg x 8 x4
8
DQ[7:0](2)
8
DQ[7:0](1)
DQ[7:0](0)
U0
SDRAM
16Meg x 8 x4
DQ[7:0](0)
2.5Gigabit (64Mx40)
3.0Gigabit (64Mx48)
Figure 1. Block Diagrams
1

 
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