IS62LV1024L
IS62LV1024L/LL
IS62LV1024LL
128K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
.EATURES
Access times of 45, 55, and 70 ns
Low active power: 60 mW (typical)
Low standby power: 15 µW (typical) CMOS
standby
Low data retention voltage: 2V (min.)
Available in Low Power (-L) and
Ultra Low Power (-LL)
Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
TTL compatible inputs and outputs
Single 2.7V to 3.6V power supply
DESCRIPTION
The
1+51
IS62LV1024L and IS62LV1024LL are low power
and low Vcc,131,072-word by 8-bit CMOS static RAMs. They
are fabricated using
1+51
's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low power
consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV1024L and IS62LV1024LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin
6*8mm T.-BGA.
.UNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 X 2048
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
1
IS62LV1024L/LL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
, I
SB
I
SB
, I
SB
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
CC
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
0.5 to Vcc + 0.5
0.3 to +4.6
40 to +85
65 to +150
0.7
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
p.
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= 1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.2
2.2
0.3
1
1
Max.
0.4
V
CC
+ 0.3
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
Notes:
1. V
IL
= 3.0V for pulse width less than 10 ns.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
3
IS62LV1024L/LL
IS62LV1024L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
-45L ns
Min. Max.
40
45
0.3
0.4
50
75
-55L ns
Min. Max.
35
40
0.3
0.4
50
75
-70L ns
Min. Max.
30
35
0.3
0.4
50
75
Unit
mA
mA
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
,
CE1
≥
V
IH
Ind.
or CE2
≤
V
IL
, f = 0
V
CC
= Max., f = 0
Com.
CE1
≥
V
CC
0.2V,
Ind.
CE2
≤
0.2V,
or V
IN
≥
V
CC
0.2V, V
IN
≤
0.2V
I
SB
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV1024LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
-45LL ns
Min. Max.
40
45
0.2
0.3
5
10
-55LL ns
Min. Max.
35
40
0.2
0.3
5
10
-70LL ns
Min. Max.
30
35
0.2
0.3
5
10
Unit
mA
mA
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
,
CE1
≥
V
IH
Ind.
or CE2
≤
V
IL
, f = 0
V
CC
= Max., f = 0
Com.
CE1
≥
V
CC
0.2V,
Ind.
CE2
≤
0.2V,
or V
IN
≥
V
CC
0.2V, V
IN
≤
0.2V
I
SB
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE1
Access Time
CE2 Access Time
OE
Access Time
Min.
45
10
0
0
5
5
0
Max.
45
45
45
20
15
15
Min.
55
10
5
0
7
7
0
-55
Max.
55
55
55
25
20
20
Min.
70
10
5
0
10
10
0
-70
Max.
70
70
70
35
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
ACE
t
DOE
t
LZOE
OE
to Low-Z Output
t
HZOE
OE
to High-Z Output
t
LZCE
CE1
to Low-Z Output
t
LZCE
CE2 to Low-Z Output
t
HZCE
CE1
or CE2 to High-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and .all Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See .igures 1
AC TEST LOADS
1 TTL
OUTPUT
100 pF
Including
jig and
scope
.igure 1.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
1 TTL
OUTPUT
5 pF
Including
jig and
scope
.igure 2.
5
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