FS401, FS403
PC to TV Video
Scan Converters
Features
†Note: Covered under US Patent # 5,862,268, #
5,905,536, # 5,966,184 and/or patents pending.
•
•
•
•
•
•
Frame rate Conversion †
Programmable 2D scaling †
Pan and Zoom †
Advanced 2-D flicker filter †
Frame-store memory controller
Supports Multiple Progressive Input
Resolutions †
–Minimum
640x 400
–Maximum
2048 x 1536
•
Supports Interlaced Input
–XGA
and above
•
Input refresh rates up to 150Hz
•
Multiple Output Standards
–NTSC,
NTSC-EIAJ, PAL-B/G/H/I †
–Composite,
S-Video, SCART
–RGB,
YUV
Standard NTSC and PAL
Super NTSC & PAL
VGA Progressive
SVGA Progressive
NTSC Progressive
PAL 100Hz Interlaced
•
Automatically detects input active video
area
•
Automatically selects the best output and
scaling for any input resolution
•
Programmable sharpness, brightness,
contrast and color saturation
•
Customizable On Screen Display via
glueless integration with Zilog and Philips
OSD Microprocessors (FS403)
•
C, H, and V Sync tri-state outputs
•
H and V Sync monitoring for DPMS
Support
•
Exceeds all PC97 and PC98 requirements
•
General Purpose Output Pins
(2 on FS401, 7 on FS403)
•
Genlock (FS403)
•
8-bit A/D converters with frequency
adaptive input filtering support
•
10-bit output D/A converters
•
Digital RGB Inputs (FS403)
•
I
2
C
‡
compatible port controls (SIO)
•
100 pin PQFP (FS401)
•
128 pin PQFP (FS403)
•
3.3V operation
•
RoHS Compliant
1
JANUARY 24, 2007
Description
The FS400 family is a fourth generation
video scan converter. It accepts many
input resolutions and rates and converts
them to NTSC or PAL standards compliant
with SMPTE-170M and CCIR-656
standards. Also available as output
options are VGA 640 x 480 at 60Hz
progressive, SVGA 800 x 600 at 60Hz
progressive, and 100 Hz interlaced. The
chip has a programmable down scaler to fit
the incoming resolution to the output
display format. Within the FS400 are
capture and encoder engines separated by
the frame buffer memory controller.
Required external components are
minimal: a single 16M SDRAM memory,
clocks and passive parts.
Analog progressive RGB inputs are
digitized and converted to the YUV 4:2:2
format. Vertical scaling and flicker filtering
are implemented at the computer frame
rate ahead of the frame store interface.
Interlaced input is supported for XGA
resolution and above. In this mode, only
the first field is processed.
The Flicker Filter is an advanced 2
dimensional filter that enhances text
quality. Flicker Filter parameters are
programmable to allow user tradeoffs
between flicker and sharpness.
The FS400 family contains controls for
programmable sharpness, brightness,
contrast, and color saturation. These
controls allow output to be tuned to match
user desires and tastes.
Frame rate conversion is
implemented by a Frame Store
Controller that interfaces with an
external SDRAM frame store
memory.
YUV 4:2:2 data is recovered from
the memory at the outgoing frame
rate. Data is scaled prior to the
COPYRIGHT
©1999,
2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
digital video encoder that generates
Y/C and Composite Video outputs.
For RGB and YUV outputs, the
encoder may be bypassed via a
YUV to RGB transcoder for SCART
compatible video, and for output to
VGA or SVGA displays.
The FS400 has built in capability to
automatically detect the incoming
video mode and automatically
select optimal sampling and scaling
parameters. The chip can detect
the location of the active video in
the input, and can automatically
center the input on the TV screen.
All parameters can be read and
written via the SIO serial port.
The FS403 has support for glueless
integration with Zilog and Philips On
Screen Display (OSD)
microcontrollers. The OSD
interface allows a customized on
screen user interface that can
contain opaque or halftone video
backgrounds.
The FS403 has direct digital inputs,
bypassing the built-in ADCs.
Power is derived from +3.3V digital
and analog supplies. Packages are
100-lead (FS401) or 128-lead
(FS403) Plastic Quad Flat Pack
(PQFP).
Applications
•
•
•
•
•
•
PC video out
PC ready TV’s
Video Text Displays
Web Appliances
PC-to-TV Scan Converter
Peripherals
Video Kiosks
Architectural Block Diagram
ADC_SEL
R_DIG
G_DIG
B_DIG
Built In
Pattern
Multiplexer
VSYNC
HSYNC
CSYNC
FLP_RST
Video
Encoder
YUV/RGB
Matrix
10 Bit
DAC
10 Bit
DAC
10 Bit
DAC
LUMA_R_V
CVBS_G_Y
CHROMA_B_U
Gain
RED
GRN
BLU
8 Bit
ADC
8 Bit
ADC
8 Bit
ADC
Vertical
Scaler
VGA
PLL
Horizontal
Scaler
/3
Flicker
Filter
VGA
Cache
TV
Cache
RGB/YUV
Matrix
OSD Overlay
Clamp
RGB_OSD
HALFTONE
VGA_HSYNC
VGA_VSYNC
Clock
Generator
DRAM
PLL
Xtal_N
Xtal_P
Serial Bus
Interface
Embedded
Processor
2
JANUARY 24, 2007
COPYRIGHT
©
1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
NTSC_PAL
SIO_DATA
4 BUTTON
SIO_CLK
EXT_CPU
SIO_10/7
SIO_A0
OSD_EN
External
Sync
DRAM
Memory
Multiplexer
FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
Contents
1.
Architectural Overview .................................... 5
1.1
Video Capture Engine............................. 5
1.2
Frame Store Memory Controller ............. 6
1.3
Video Encoder Engine ............................ 6
1.4
Serial Control Port .................................. 6
1.5
Typical System Configurations ............... 7
1.5.1 External Scan Converter .................... 7
1.5.2 Embedded Television Interface.......... 8
1.5.3 Deleted ............................................... 8
1.5.4 Professional and Pro-Consumer
Video Designs ................................................. 9
2.
Pin Assignments............................................ 10
2.1
100-Lead PQFP Package (FS401)....... 10
2.2
128-Lead PQFP Package (FS403)....... 11
3.
Pin Descriptions ............................................ 12
4.
Control Register Definitions........................... 17
4.1
Control Register Functions ................... 17
4.2
Internal Micro-Controller
Programming ..................................................... 18
4.2.1 Input Calibration ............................... 18
4.2.1.1
Auto Input Calibration .............. 18
4.2.1.2
Manual Input Calibration.......... 19
4.2.1.3
Input Calibration Tables........... 20
4.2.2 Output Calibration ............................ 20
4.2.3 Zoom ................................................ 20
4.2.4 Panning ............................................ 21
4.2.5 Picture Control.................................. 21
4.2.6 Video Mode Changes....................... 22
4.2.7 By-passing the Internal Micro-
Controller ....................................................... 22
4.2.8 Special Internal Micro-Controller
SIO Requirements......................................... 24
4.3
Disabling the Internal Micro-
Controller ........................................................... 24
4.4
Control Register Definitions.................. 25
4.5
Control Registers Definitions ................ 28
4.5.1 IHO - Input Horizontal Offset ............ 28
4.5.2 IVO - Input Vertical Offset ................ 29
4.5.3 IHAW - Horizontal Active Width ....... 30
4.5.4 ILS - Input Lines Stored.................... 31
4.5.5 IHS - Input Horizontal Samples........ 32
4.5.6 IHC - Input Horizontal Count ............ 33
4.5.7 IVC - Input Vertical Count................. 34
4.5.8 VSC – Vertical Scaling Coefficient ... 35
4.5.9 CR - Command Register .................. 36
4.5.10
SR – Status Register ................... 37
4.5.11
CRE – Command Register
Extended 38
4.5.12
Start Horizontal Active VGA......... 39
4.5.13
End Horizontal Active VGA .......... 40
4.5.14
Start Vertical Active VGA ............. 41
4.5.15
End Vertical Active VGA .............. 42
4.5.16
Active Video Threshold ................ 43
4.5.17
OHO - Output Horizontal Offset ... 44
4.5.18
OVO – Output Vertical Offset....... 45
4.5.19
HSC – Horizontal Scaling
Coefficient 46
3
JANUARY 24, 2007
COPYRIGHT
©
1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
4.5.20
Contrast Coefficient ......................47
4.5.21
Brightness Coefficient...................48
4.5.22
Sharpness Coefficient ..................49
4.5.23
Flicker Filter Coefficient ................50
4.5.24
Color Saturation Coefficient..........51
4.5.25
General Purpose Outputs.............52
4.5.26
SCR – Software Control
Register 53
4.5.27
SSR – Software Status Register ..55
4.5.28
HCRS – Hardware Control
Register Shadow............................................56
4.5.29
HCRES – Hardware Control
Register Extended Shadow ...........................57
4.5.30
HPO – Horizontal Position
Offset
58
4.5.31
VPO – Vertical Position Offset......59
4.5.32
HSS – Horizontal Scale Step........60
4.5.33
VSS – Vertical Scale Step ............61
4.5.34
HPP – Horizontal Pan Position.....62
4.5.35
VPP – Vertical Pan Position .........63
4.5.36
TVP – TV Pixels............................64
4.5.37
TVL – TV Lines .............................65
4.5.38
CCR – Configuration Command
Register 66
4.5.39
CDR – Configuration Data
Register 67
4.5.40
HOHOS – Hardware Output
Horizontal Offset Shadow ..............................68
4.5.41
HOVOS – Hardware Output
Vertical Offset Shadow...................................69
4.6
Configuration Values .............................70
Addr ....................................................................70
5.
Functional Description ...................................75
5.1
Capture Engine .....................................75
5.1.1 Timing and Control............................75
5.1.2 Clamps ..............................................76
5.1.3 Analog-to-Digital Converters.............76
5.1.4 24-bit Digital RGB Port (FS403
only) 77
5.1.5 Built In Pattern Generator .................77
5.1.6 Digital RGB Multiplexer .....................78
5.1.7 RGB Gain..........................................78
5.1.8 RGB/YUV Matrix ...............................78
5.1.9 Vertical Scaler ...................................78
5.1.10
Flicker Filter ..................................78
5.2
Frame Store Controller..........................80
5.2.1 SDRAM Interface ..............................81
5.2.2 Phase Locked Loop ..........................81
5.2.3 Input Offset and Size Control............81
5.2.4 Output Offset and Size Control .........82
5.2.5 Freeze Frame....................................82
5.2.6 Zoom .................................................83
5.3
Encoder Engine .....................................83
5.3.1 Timing and Control............................83
5.3.2 Horizontal Scaler...............................84
5.3.3 Digital Video Encoder .......................84
5.3.4 YUV/RGB Matrix ...............................84
FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
5.3.5 Digital-to-Analog Converters ............ 85
5.3.6 On-Screen Display (FS403 only) ..... 85
5.4
Serial Control Port (R-Bus)................... 85
5.4.1 Data Transfer via Serial Interface .... 88
5.4.2 Serial Interface Read/Write
Examples....................................................... 88
5.4.2.1
Write to one control register .... 88
5.4.2.2
Write to two consecutive
control registers......................................... 89
5.4.2.3
Read from one control
register 89
5.4.2.4
Read from two consecutive
data registers ............................................ 89
5.5
Embedded Microprocessor................... 89
6.
Specifications ................................................ 90
6.1
Absolute Maximum Ratings.................. 90
6.2
Operating Conditions ............................ 91
6.3
Electrical Characteristics ...................... 92
6.4
Switching Characteristics ..................... 93
6.5
System Performance Characteristics ... 94
7.
Application Notes .......................................... 95
7.1
Circuit Example - PC ............................ 95
7.2
FS400 Design and Layout
Considerations................................................... 96
7.2.1 Video Input to A-D Converters ......... 96
7.2.2 Input ADC Phase Lock Loop............ 96
7.2.3 Memory Clock Phase Lock Loop ..... 96
7.2.4 External SDRAM Interface ............... 96
7.2.5 HSYNC and VSYNC ........................ 96
7.2.6 Video Output Filters.......................... 97
7.2.7 Analog Power Supply Bypassing,
Filtering, and Isolation ................................... 97
7.2.8 Power and Ground ........................... 97
7.3
Interfacing to the FS400 in a Mixed
Voltage Environment ......................................... 98
7.3.1 5 to 3.3 Volt Translation ................... 98
7.3.2 SIO Bus Interfacing .......................... 98
8.
Mechanical Dimensions .............................. 101
8.1
100-Lead PQFP (KH) Package -
FS401LF .......................................................... 101
8.2
128-Lead PQFP Package, FS403 LF. 102
9.
Revision History .......................................... 103
10.
Ordering Information ............................... 104
10.1
Package Markings: ............................. 104
Figures
Figure 1: External Scan Converter Block
Diagram............................................................7
Figure 2: Embedded Television Design Block
Diagram............................................................8
Figure 3: Deleted .....................................................8
Figure 4: Professional & Pro-Consumer Video
Design Block Diagram .....................................9
Figure 5. Functional Block Diagram ......................75
Figure 6. FAZE Sets ADCK Sampling Edge on
Incoming Pixels ..............................................77
Figure 7: BiPGEN Image .......................................77
Figure 8: Two Dimensional Flicker Filter
Response (FLK=0,4,8,12,16,20; SHP=0) ......79
Figure 9: FLK = 16, SHP = 8; Response at
Horizontal, 14, 27, 45 Degrees ......................79
Figure 10: FLK = 16, SHP = 16; Response at
Horizontal, 14, 27, 45 Degrees ......................80
Figure 11. Timing Parameter Definition, SDRAM
Interface .........................................................81
Figure 12. Input Offset and Size Definitions ..........82
Figure 13. Output Horizontal and Vertical Offset
Definitions ......................................................82
Figure 14. Zoomed image showing offsets............83
Figure 15. R
REF
and V
TIN
Setup..............................85
Figure 16. Serial Port Read/Write Timing..............86
Figure 17. Serial Interface – Typical Byte
Transfer ..........................................................86
Figure 18. 7-bit Slave Address with Read/Write\
Bit ...................................................................87
Figure 19. 10-bit address transfer, upper two
bits..................................................................87
Figure 20. 10-bit address transfer, lower eight
bits..................................................................87
Figure 21. Video Filter Response ..........................95
Figure 22. Video Filter Delay .................................95
Figure 23. 5 to 3.3 Volt Translation using a
Resistor ..........................................................98
Figure 24. 5 to 3.3 Volt Translation using a
MOSFET Q1 = BSS138, D1 = 1N4148..........98
Figure 25. SIO Translation Using Long-tail
Resistors D1 = 1N4148..................................99
Figure 26. SIO Translation Using Current
Mirrors D1 = 1N4148, Q1 = 2N3906, Q2 =
2N3904...........................................................99
Figure 27. SIO (Open Collector) Translation
using a MOSFET Q1 = BSS138 ..................100
Tables
Table 1. Pin Designations (FS401, 100-pin
package)........................................................ 10
Table 2. Pin Designations (FS403, 128-pin
package)........................................................ 11
Table 3. Control Register Map .............................. 25
Table 4. Clock Connections ................................... 83
Table 5. Serial Port Addresses .............................. 88
4
JANUARY 24, 2007
COPYRIGHT
©
1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
1. Architectural Overview
Overall design principles are included in this section. Details of how to use and setup the FS400 are included in
the
Functional Description
section, starting on
page 75.
RGB video inputs are asynchronously converted to either NTSC/PAL, YUV or RGB video formats. Architecturally,
the FS400 is divided into five major sections:
1.
2.
3.
4.
5.
Video Capture Engine
Clock Processor
Frame Store Controller
Video Encoder Engine
Serial Bus Interface
Besides power and a few external passive components, the FS400 requires only a single 16M external SDRAM
and external clocks to implement a high quality video scan converter.
Either analog or digital inputs (FS403 only) with separate horizontal and vertical sync signals are accepted.
Analog VGA video must be RGB. Digital video (FS403 only) must be 24-bit RGB clocked by external clock,
VGACK_IN.
A wide range of resolution formats can be accepted, including common standards such as 320x240, 640x400,
720x400, 640x480, 800x600, 832x624, 1024x768, 1152x864, 1280x1024, and 1600x1200. Incoming RGB
signals are converted to either the NTSC or PAL TV Standards, 100Hz PAL, or progressive scan VGA, SVGA, or
NTSC. Output video format can be selected to be either composite and Y/C (NTSC and PAL only), or RGB or
YUV (all standards).
Incoming frame rate may range to over 150 Hz according to the table below. The Video Capture engine runs
asynchronously relative to the Video Encoder Engine. An external frame store memory separates the two
engines with write and read access controlled by the FS400.
Transformation operations include overscan, underscan, pan and zoom. Scaling operations are separated by the
frame store with vertical down-sampling incorporated into the Capture Engine and horizontal up-sampling
incorporated into the Encoder Engine.
1.1 Video Capture Engine
Triple 8-bit A/D converters digitize the analog RGB inputs at rates of up to 50 MHz. Internal A/D sample clock,
ADCK is derived from a phase locked loop referenced to the leading edge of horizontal sync. Either positive or
negative sync polarity is accepted.
The selected input (A/D converter outputs or digital RGB) is transcoded by the color matrix into a 16-bit YC
R
C
B
4:2:2 format. A vertical scaler filters the number of incoming video lines by the selected scaling factor. A flicker
filter averages lines to eliminate flicker between lines or boundaries.
The Video Capture Engine is programmable as to the number of horizontal samples it takes. The limiting factor in
the sample rate is the A/D Converters. By programming fewer samples per line, higher incoming data rates can
be accommodated. The following table illustrates the capability:
Active Samples
Maximum Line Frequency
640 x 480
800 x 600
1024 x 768
1152 x 864
1280 x 1024
1600 x 1200
720 CCIR 601
56kHz
106Hz
89Hz
70Hz
59Hz
53Hz
44Hz
640
63kHz
119Hz
100Hz
78Hz
66Hz
59Hz
50Hz
500
80kHz
152Hz
128Hz
100Hz
85Hz
76Hz
64Hz
5
JANUARY 24, 2007
COPYRIGHT
©1999,
2000, 2003 FOCUS ENHANCEMENTS, INC.
ADI 工业技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
