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DECLDL-2-18J

产品描述Active Delay Line, 2-Func, Complementary Output, ECL, PDMA8, MODULE-12/8
产品类别逻辑    逻辑   
文件大小37KB,共1页
制造商Engineered Components Co
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DECLDL-2-18J概述

Active Delay Line, 2-Func, Complementary Output, ECL, PDMA8, MODULE-12/8

DECLDL-2-18J规格参数

参数名称属性值
厂商名称Engineered Components Co
包装说明,
Reach Compliance Codeunknown
系列100K
JESD-30 代码R-PDMA-J8
逻辑集成电路类型ACTIVE DELAY LINE
功能数量2
端子数量8
最高工作温度85 °C
最低工作温度
输出极性COMPLEMENTARY
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式MICROELECTRONIC ASSEMBLY
可编程延迟线NO
表面贴装YES
技术ECL
温度等级OTHER
端子形式J BEND
端子位置DUAL
总延迟标称(td)18 ns
Base Number Matches1

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Dual 100K ECL Logic Delay Line
The Dual 100K ECL Logic Delay Lines manufactured by Engineered Components Company are designed to
provide an output waveform that reproduces the input waveform after a set amount of delay time has elapsed.
These delay lines provide both inverting and non-inverting outputs. The delay times are calibrated to the
listed tolerances on the rising edge delays at the non-inverting outputs. Each module consists of 2 separate
delay lines, each isolated and individually buffered.
The MTBF on these modules, when calculated per MIL-HDBK-217, for a 50 deg.C ground fixed environment and
with 50VDC applied, is in excess of 1.0 million hours. The temperature coefficient of delay is less than
150 ppm/deg.C over the operating temperature range of 0 to +85 deg. C.
The module is provided in a 12-pin DIP package, fully encapsulated in epoxy resin and is housed in a Diallyl
Phthalate case, blue in color. The case marking is applied by silkscreen using white epoxy paint. The 8 copper
leads are tin-lead plated and meet the solderability requirements of MIL-STD-202, Method 208.
BLOCK DIAGRAM
4
12
MECHANICAL DIAGRAM
.020
DIA.
TYP.
.350 TYP.
.700
V
IN1
IN2
Input
Buffer
Input
Buffer
Delay
Line
Delay
Line
Output
Buffer
Output
Buffer
8
7
5
6
9
OUT1
OUT1
OUT2
OUT2
Ve
1
.250
.060 TYP.
TYP.
.050 TYP.
.100 TYP.
IN
1
.875
Product Selection Table
(Add Suffixes for Lead designation, F, G, or J)
Product Selection Table (Cont.)
(Add Suffixes for Lead designation, F, G, or J)
Part
Number
DECLDL-2-2
DECLDL-2-2.5
DECLDL-2-3
DECLDL-2-3.5
DECLDL-2-4
DECLDL-2-4.5
DECLDL-2-5
DECLDL-2-5.5
DECLDL-2-6
DECLDL-2-6.5
DECLDL-2-7
DECLDL-2-7.5
DECLDL-2-8
DECLDL-2-8.5
DECLDL-2-9
DECLDL-2-9.5
Output Delay and
Tolerance (in ns)
2.0+/-0.2
2.5+/-0.2
3.0+/-0.3
3.5+/-0.3
4.0+/-0.4
4.5+/-0.4
5.0+/-0.5
5.5+/-0.5
6.0+/-0.6
6.5+/-0.6
7.0+/-0.7
7.5+/-0.7
8.0+/-0.8
8.5+/-0.8
9.0+/-0.9
9.5+/-0.9
Part
Output Delay and
Number
Tolerance (in ns)
DECLDL-2-10
10.0+/-1.0
DECLDL-2-10.5
10.5+/-1.0
DECLDL-2-11
11.0+/-1.0
DECLDL-2-11.5
11.5+/-1.0
DECLDL-2-12
12.0+/-1.0
DECLDL-2-12.5
12.5+/-1.0
DECLDL-2-13
13.0+/-1.0
DECLDL-2-13.5
13.5+/-1.0
DECLDL-2-14
14.0+/-1.0
DECLDL-2-14.5
14.5+/-1.0
DECLDL-2-15
15.0+/-1.0
DECLDL-2-16
16.0+/-1.0
DECLDL-2-17
17.0+/-1.0
DECLDL-2-18
18.0+/-1.0
DECLDL-2-19
19.0+/-1.0
DECLDL-2-20
20.0+/-1.0
IN
2
Operating Specifications:
All measurements made at 25 deg. C
All measurements made with Vee = -4.5VDC, Vcc = 0VDC
All measurements made with (1) 100K ECL output load
All measurements made with a 50 ohm pulldown
resistor to -2VDC at the input and output
Operating Temperature: 0 to +85 deg. C
Storage Temperature: -55 to +125 deg. C
Vcc Supply Voltage: -4.5 +/-5% VDC
Vee Supply Current: 155mA typical
Logic “High” Input:
Voltage: -1.165VDC min.
Current: 350uA max.
Logic “Low” Input:
Voltage: -1.475VDC max.
Current: 0.5uA min.
Logic “High” Voltage Out: -1.025VDC min.
Logic “Low” Voltage Out: -1.620VDC max.
Special modules can often be manufactured to provide for customer specific applications.
engineered components company
A Division of Cornucopia Tool & Plastics, Inc. PO Box 1915, 448 Sherwood Rd., Paso Robles CA 93447
YYWW
Ve O
1
O
1
.325
MADE IN USA
.030
TYP.
DATE CODE
+/-.030
.160
DECLDL-2-10
Top view
V O
2
O
2
.700
Phone: 805-369-0034
Fax:
805-369-0033
Web: www.ec2.com

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