74AHC1G00-Q100;
74AHCT1G00-Q100
2-input NAND gate
Rev. 1 — 16 September 2013
Product data sheet
1. General description
74AHC1G00-Q100 and 74AHCT1G00-Q100 are high-speed Si-gate CMOS devices.
They provide a 2-input NAND function.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
SOT353-1 and SOT753 package options
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC1G00GW-Q100
74AHCT1G00GW-Q100
74AHC1G00GV-Q100
74AHCT1G00GV-Q100
40 C
to +125
C
SC-74A
40 C
to +125
C
Name
TSSOP5
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
Version
SOT353-1
Type number
plastic surface-mounted package; 5 leads SOT753
NXP Semiconductors
74AHC1G00-Q100; 74AHCT1G00-Q100
2-input NAND gate
4. Marking
Table 2.
Marking codes
Marking
AA
A00
CA
C00
Type number
74AHC1G00GW-Q100
74AHCT1G00GW-Q100
74AHC1G00GV-Q100
74AHCT1G00GV-Q100
5. Functional diagram
B
1
2
B
A
1
Y
4
2
mna097
mna098
&
4
A
Y
mna099
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
Fig 4. Pin configuration
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
V
CC
Pin description
Pin
1
2
3
4
5
Description
data input
data input
ground (0 V)
data output
supply voltage
74AHC_AHCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
2 of 12
NXP Semiconductors
74AHC1G00-Q100; 74AHCT1G00-Q100
2-input NAND gate
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
20
25
75
-
+150
250
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
20
-
-
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For both TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
74AHC1G00-Q100
Min
2.0
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74AHCT1G00-Q100
Min
4.5
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
C
ns/V
ns/V
Unit
74AHC_AHCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
3 of 12
NXP Semiconductors
74AHC1G00-Q100; 74AHCT1G00-Q100
2-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
For type 74AHC1G00-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
1.5
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
1.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
10
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
For type 74AHCT1G00-Q100
V
IH
V
IL
V
OH
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
50 A
I
O
=
8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
A
I
O
= 8.0 mA
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
4.4
3.94
-
-
-
4.5
-
0
-
-
-
-
0.1
0.36
0.1
4.4
3.8
-
-
-
-
-
0.1
0.44
1.0
4.4
3.70
-
-
-
-
-
0.1
0.55
2.0
V
V
V
V
A
V
OL
I
I
74AHC_AHCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
4 of 12
NXP Semiconductors
74AHC1G00-Q100; 74AHCT1G00-Q100
2-input NAND gate
Table 7.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
I
CC
Conditions
Min
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin; V
I
= 3.4 V;
supply current other inputs at V
CC
or GND;
I
O
= 0 A; V
CC
= 5.5 V
input
capacitance
-
-
25
C
Typ
-
-
Max
1.0
1.35
40 C
to +85
C 40 C
to +125
C
Unit
Min
-
-
Max
10
1.5
Min
-
-
Max
40
1.5
A
mA
C
I
-
1.5
10
-
10
-
10
pF
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; t
r
= t
f
=
3.0 ns. For test circuit, see
Figure 6.
Symbol Parameter
Conditions
Min
For type 74AHC1G00-Q100
t
pd
propagation
delay
A and B to Y; see
Figure 5
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
propagation
delay
per buffer;
C
L
= 50 pF; f = 1 MHz;
V
I
= GND to V
CC
A and B to Y;
see
Figure 5;
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
per buffer;
V
I
= GND to V
CC
[4]
[4]
[3]
[1]
[2]
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
-
-
-
-
-
4.5
6.5
3.5
4.9
17
7.9
11.4
5.5
7.5
-
1.0
1.0
1.0
1.0
-
9.5
13.0
6.5
8.5
-
1.0
1.0
1.0
1.0
-
10.5
14.5
7.0
9.5
-
ns
ns
ns
ns
pF
For type 74AHCT1G00-Q100
t
pd
[1]
[3]
-
-
-
3.6
5.0
18
6.2
7.9
-
1.0
1.0
-
7.1
9.0
-
1.0
1.0
-
8.0
10.0
-
ns
ns
pF
[1]
[2]
[3]
[4]
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at V
CC
= 3.3 V.
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation P
D
(W).
P
D
= C
PD
V
CC2
f
i
+
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
74AHC_AHCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
5 of 12
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
