74AHC04; 74AHCT04
hex inverter
Rev. 6 — 7 November 2011
Product data sheet
1. General description
The 74AHC04; 74AHCT04 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC04; 74AHCT04 provides six inverting buffers.
2. Features and benefits
Balanced propagation delays
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC04: CMOS level
For 74AHCT04: TTL level
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC04
74AHC04D
74AHC04PW
74AHC04BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
Name
Description
Version
Type number
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
SOT762-1
NXP Semiconductors
74AHC04; 74AHCT04
hex inverter
Table 1.
Ordering information
…continued
Package
Temperature range
Name
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
Type number
74AHCT04
74AHCT04D
74AHCT04PW
74AHCT04BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
SOT762-1
4. Functional diagram
1
1
2
1
1A
1Y
2
3
1
4
3
2A
2Y
4
5
1
6
5
3A
3Y
6
9
1
8
9
4A
4Y
8
11
5A
5Y
10
11
1
10
13
6A
6Y
12
13
1
mna343
12
mna342
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
Y
mna341
Fig 3.
Logic diagram (one inverter)
74AHC_AHCT04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2011
2 of 15
NXP Semiconductors
74AHC04; 74AHCT04
hex inverter
5. Pinning information
5.1 Pinning
terminal 1
index area
1Y
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
001aac441
2
3
4
5
6
7
GND
4Y
8
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
4A
14 V
CC
13 6A
12 6Y
2A
2Y
3A
3Y
04
11 5A
10 5Y
9
8
4A
4Y
GND
(1)
1
1A
04
001aac442
Transparent top view
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It can not be used
as a supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
GND
V
CC
Pin description
Pin
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13
6. Functional description
Table 3.
Input nA
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output nY
H
L
74AHC_AHCT04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2011
3 of 15
NXP Semiconductors
74AHC04; 74AHCT04
hex inverter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<0.5 V or V
O
> V
CC
+ 0.5 V
V
O
=0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
74AHC04
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74AHCT04
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 4.5 V to 5.5 V
4.5
0
0
40
-
5.0
-
-
+25
-
5.5
5.5
V
CC
+125
20
V
V
V
C
ns/V
2.0
0
0
40
-
-
5.0
-
-
+25
-
-
5.5
5.5
V
CC
+125
100
20
V
V
V
C
ns/V
ns/V
Operating conditions
Conditions
Min
Typ
Max
Unit
Symbol Parameter
74AHC_AHCT04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2011
4 of 15
NXP Semiconductors
74AHC04; 74AHCT04
hex inverter
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC04
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
I
= V
CC
or GND
74AHCT04
V
IH
V
IL
V
OH
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
50 A
I
O
=
8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
A
I
O
= 8.0 mA
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
4.4
3.94
-
-
-
4.5
-
0
-
-
-
-
0.1
0.36
0.1
4.4
3.80
-
-
-
-
-
0.1
0.44
1.0
4.4
3.70
-
-
-
-
-
0.1
0.55
2.0
V
V
V
V
A
V
OL
I
I
74AHC_AHCT04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2011
5 of 15
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