specified for the extended temperature range of –40 to
85°C.
The ASM2I99456 is a full static design supporting clock
frequencies up to 250 MHz. The signals are generated and
retimed on-chip to ensure minimal skew between the three
output banks.
Each of the three output banks can be individually supplied
by 2.5V or 3.3V supporting mixed voltage applications. The
FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set
individually for each of the three output banks. The
ASM2I99456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. The clock input is
low
voltage
PECL
compatible
for
differential
clock
distribution support. Please consult the ASM2I99446
specification for a full CMOS compatible device. For series
terminated transmission lines, each of the ASM2I99456
outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a
7x7 mm
2
32-lead LQFP and TQFP Packages.
Functional Description
The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-Voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99456
offers 10 low-skew outputs and a differential LVPECL clock
input. The outputs are configurable and support 1:1 and 1:2
output to input frequency ratios. The ASM2I99456 is
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.2
Block Diagram
Bank A
PCLK
PCLK
VCC/2
25K
Bank B
0
1
25K
CLK
CLK÷ 2
0
1
ASM2I99456
QA0
QA1
QA2
QB0
QB1
QB2
FSELA
25K
FSELB
25K
FSELC
MR/OE
0
1
25K
25K
Bank C
QC0
QC1
QC2
QC3
ASM2I99456 Logic Diagram
Pin Configuration
VCCC
VCCB
VCCB
GND
GND
QB0
QB1
QB2
VCCB is internally connected to VCC
24
VCCA
QA2
GND
QA1
VCCA
QA0
GND
MR/OE
25
26
27
28
29
30
31
32
1
23
22
21
20
19
18
17
16
15
14
QC3
GND
QC2
VCCC
QC1
GND
QC0
VCCC
ASM2I99456
13
12
11
10
9
2
3
4
5
6
7
8
PECL_CLK
PCL_CLK
FSELB
FSELA
FSELC
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
GND
NC
VCC
2 of 14
June 2005
rev 0.2
Table 1. Pin Configuration
Pin Number
3
4
5,6,7
32
8,11,15,20,24,27,31
25,29
18,22
9,13, 17
2
30,28,26
23,21,19
10,12,14,16
1
ASM2I99456
Pin
PECL_CLK,
PECL_CLK
FSELA, FSELB,
FSELC
MR/OE
GND
VCCA,
VCCB
1
,
VCCC
VCC
QA0 - QA2
QB0 - QB2
QC0 - QC3
NC
I/O
Input
Input
Input
Type
LVPECL
LVCMOS
LVCMOS
Supply
Supply
Supply
Function
Differential Clock reference
Low Voltage positive ECL input
Output bank divide select input
Internal reset and output tristate control
Negative Voltage supply output bank (GND)
Positive Voltage supply for output banks
Positive Voltage supply core (VCC)
Bank A Outputs
Bank B Outputs
Bank C Outputs
No Connect
Output
Output
Output
-
LVCMOS
LVCMOS
LVCMOS
-
Note:1 VCCB is internally connected to VCC.
Table 2. Supported Single and Dual Supply Configurations
Supply voltage
configuration
3.3V
Mixed voltage supply
2.5V
VCC
1
3.3V
3.3V
2.5V
VCCA
2
3.3V
3.3V or 2.5V
2.5V
VCCB
3
3.3V
3.3V
2.5V
VCCC
4
3.3V
3.3V or 2.5V
2.5V
GND
0V
0V
0V
Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels
2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels
3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.
4 VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels
Table 3. Function Table (Controls)
Control
FSELA
FSELB
FSELC
MR/OE
Default
0
0
0
0
f
QA0:2
= f
REF
f
QB0:2
= f
REF
f
QC0:3
= f
REF
Outputs enabled
0
1
f
QA0:2
= f
REF
÷2
f
QB0:2
= f
REF
÷2
f
QC0:3
= f
REF
÷2
Internal reset
Outputs disabled (tristate)
Table 4. Absolute Maximum Ratings
1
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-40
Characteristics
Min
-0.3
-0.3
-0.3
Max
4.6
V
CC
+0.3
V
CC
+0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
3 of 14
June 2005
rev 0.2
Table 5. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
ASM2I99456
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
Power Dissipation Capacitance
Input Capacitance
Min
200
2000
200
Typ
VCC ÷2
Max
Unit
V
V
V
mA
Condition
10
4.0
pF
pF
Per output
Table 6. DC Characteristics
(VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, T
A
= –40 to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR1
I
IN
V
OH
V
OL
Z
OUT
I
CCQ4
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
Input current
2
Output High Voltage
Output Low Voltage
Output impedance
Maximum Quiescent Supply Current
PCLK
PCLK
Min
2.0
-0.3
250
1.1
Typ
Max
VCC + 0.3
0.8
VCC-0.6
200
Unit
V
V
mV
V
µA
V
V
V
Ω
mA
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
V
IN
=GND or
V
IN
=VCC
I
OH
=-24 mA
3
I
OL
= 24mA
2
I
OL
= 12mA
All VCC Pins
2.4
0.55
0.30
14 - 17
2.0
Note: 1 V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
3 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
4 I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
4 of 14
June 2005
rev 0.2
Table 7. AC Characteristics
(VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, T
A
= –40 to +85°C)
1
Symbol
f
ref
f
MAX
V
PP
V
CMR3
t
P
,
REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ
,
HZ
t
PZL
,
LZ
t
sk(O)
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
ASM2I99456
Characteristics
Input Frequency
Maximum Output
Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-device Skew
Output pulse skew
5
Output Duty Cycle
Output Rise/Fall Time
÷1 output
÷2 output
CCLK to any Q
CCLK to any Q
÷1 output
÷2 output
PCLK
PCLK
Min
0
0
0
500
1.3
1.4
Typ
Max
250
2
2
Unit
MHz
MHz
MHz
mV
V
nS
nS
nS
nS
nS
nS
pS
pS
pS
nS
pS
%
%
nS
Condition
FSELx=0
FSELx=1
LVPECL
LVPECL
0.8 to 2.0V
250
125
1000
VCC-0.8
1.0
4
2.2
2.2
2.8
2.8
4.45
4.2
10
10
150
200
350
2.25
200
47
45
0.1
50
50
53
55
1.0
DC
REF
= 50%
DC
REF
= 25%-75%
0.55 to 2.4V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to V
TT
.
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
- t
PHL
|.
Table 8. DC Characteristics
(VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T
A
= –40 to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR1
V
OH
V
OL
Z
OUT
I
IN
I
CCQ
4
Characteristics
Input high voltage
Input low voltage
Peak-to-peak Input voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output impedance
Input current
Maximum Quiescent Supply Current
3
Min
1.7
-0.3
PCLK
PCLK
250
1.1
1.8
Typ
Max
V
CC
+ 0.3
0.7
V
CC
-0.7
0.6
Unit
V
V
mV
V
V
V
Ω
µA
mA
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
=-24 mA
2
I
OL
= 15 mA
V
IN
=GND or V
IN
=V
CC
All VCC Pins
17 - 20
2
±200
2.0
Note:1 V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(DC) specification.
2 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
运行结果提示：the arc between pins 'CK' and 'D' is negative, which is not allowed. To make it positive, the maximum hold value has been adjusted from 0.729405 to 0.782819.请问：1. ......
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