74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 02 — 7 February 2005
Product data sheet
1. General description
The 74ABT823 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data and address paths
of buses carrying parity.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master
reset input (MR) which are ideal for parity bus interfacing in systems using many
microprocessors.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
2. Features
s
High-speed parallel registers with positive edge-triggered D-type flip-flops
s
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
s
Output capability: +64 mA and
−32
mA
s
Latch-up protection:
x
JESD78: exceeds 500 mA
s
ESD protection:
x
MIL STD 883 method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
s
Power-on 3-state
s
Power-on reset
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
I
C
O
I
CC
propagation delay CP to Qn
propagation delay CP to Qn
input capacitance
output capacitance
quiescent supply current
Conditions
C
L
= 50 pF; V
CC
= 5 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
outputs disabled;
V
O
= 0 V or V
CC
outputs 3-state;
V
CC
= 5.5 V;
V
I
= GND or V
CC
Min
-
-
-
-
-
Typ
4.3
4.4
4
7
0.5
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
µA
Philips Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74ABT823N
74ABT823D
74ABT823DB
74ABT823PW
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
DIP24
SO24
SSOP24
TSSOP24
Description
plastic dual in-line package; 24 leads (300 mil)
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT222-1
SOT137-1
SOT340-1
SOT355-1
Type number
5. Functional diagram
1
11
11
2
3
4
5
6
7
8
9
10
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
CP
13
1
14
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
14
001aaa847
EN
R
G1
1C2
23
22
21
20
19
18
17
16
15
001aaa848
23
22
21
20
19
18
17
16
15
13
2
3
4
5
6
7
8
9
10
2D
Fig 1. Logic symbol
Fig 2. IEC logic symbol
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
2 of 19
Philips Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
D0
D1
D2
D3
D4
MR
R
R
R
R
R
CE
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF0
CP
FF1
CP
FF2
CP
FF3
CP
FF4
CP
OE
Q0
D5
D6
Q1
D7
Q2
D8
Q3
Q4
D
R
Q
D
R
Q
D
R
Q
D
R
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
Q5
Q6
Q7
Q8
001aac444
Fig 3. Logic diagram
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
3 of 19
Philips Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
6. Pinning information
6.1 Pinning
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
13 CP
001aaa845
823
D8 10
MR 11
GND 12
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
CP
CE
Q8
Q7
Q6
Q5
Q4
Q3
Q2
9397 750 14551
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Description
output enable input (active LOW)
data input 0
data input 1
data input 2
data input 3
data input 4
data input 5
data input 6
data input 7
data input 8
master reset input (active LOW)
ground (0 V)
clock pulse input (active rising edge)
clock enable input (active LOW)
data output 8
data output 7
data output 6
data output 5
data output 4
data output 3
data output 2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
4 of 19
Philips Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Pin description
…continued
Pin
22
23
24
Description
data output 1
data output 0
positive supply voltage
Table 3:
Symbol
Q1
Q0
V
CC
7. Functional description
7.1 Function table
Table 4:
Function table
[1]
Input
OE
Clear
L
Load and read data L
Hold
High-impedance
[1]
Operating mode
Output
MR
L
H
H
X
CE
X
L
H
X
CP
X
↑
NC
X
Dn
X
h
l
X
X
Qn
L
H
L
NC
Z
L
H
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑
= LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
5 of 19
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