74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Rev. 03 — 20 April 2005
Product data sheet
1. General description
The 74ABT544 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch enable (LEAB and LEBA) and
output enable (OEAB and OEBA) inputs are provided for each register to permit
independent control of data transfer in either direction. The outputs are guaranteed to sink
64 mA.
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for
each set. Using data flow from A to B as an example, when the A-to-B enable (EAB) input
and the A-to-B latch enable (LEAB) input are LOW, the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA and OEBA inputs.
2. Features
s
s
s
s
s
s
s
s
s
Combines 74ABT640 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64 mA and
−32
mA
Live insertion and extraction permitted
Power-up 3-state
Power-up reset
Latch-up protection:
x
JESD78: exceeds 500 mA
s
ESD protection:
x
MIL STD 883 method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
3. Quick reference data
Table 1:
Quick reference data
T
amb
= 25
°
C; GND = 0 V.
Symbol Parameter
t
PLH
t
PHL
C
I
C
I/O
I
CC
propagation delay An
to Bn or Bn to An
propagation delay An
to Bn or Bn to An
input capacitance
I/O capacitance
quiescent supply
current
Conditions
C
L
= 50 pF; V
CC
= 5 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
outputs disabled; V
O
= 0 V or V
CC
outputs 3-state; V
CC
= 5.5 V
Min
-
-
-
-
-
Typ
3.0
3.6
4
7
110
Max Unit
-
-
-
-
-
ns
ns
pF
pF
µA
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74ABT544D
74ABT544N
74ABT544DB
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO24
DIP24
SSOP24
TSSOP24
Description
plastic dual in-line package; 24 leads (300 mil)
plastic shrink small outline package; 24 leads; body width
5.3 mm
plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
Version
SOT222-1
SOT340-1
SOT355-1
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
Type number
74ABT544PW
−40 °C
to +85
°C
5. Functional diagram
2
23
1
13
11
14
3
13
2
4
5
6
7
22 21 20 19 18 17 16 15
001aac756
3
4
5
6
7
8
9
10
1EN3 (AB)
G1
1C5
2EN4 (BA)
G2
2C6
3
5D
5D
4
21
20
19
18
17
16
15
001aac757
11
23
14
1
A0 A1 A2 A3 A4 A5 A6 A7
EAB
EBA
LEAB
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
OEAB
OEBA
22
8
9
10
Fig 1. Logic symbol
Fig 2. IEC logic symbol
9397 750 14756
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 20 April 2005
2 of 19
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
6. Pinning information
6.1 Pinning
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
24 V
CC
23 EBA
22 B0
21 B1
20 B2
19 B3
544
7
8
9
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
001aac755
A7 10
EAB 11
GND 12
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
EAB
GND
OEAB
LEAB
B7
B6
B5
B4
9397 750 14756
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
B-to-A latch enable input (active LOW)
B-to-A output enable input (active LOW)
port A, 3-state output 0
port A, 3-state output 1
port A, 3-state output 2
port A, 3-state output 3
port A, 3-state output 4
port A, 3-state output 5
port A, 3-state output 6
port A, 3-state output 7
A-to-B enable input (active LOW)
ground (0 V)
A-to-B output enable input (active LOW)
A-to-B latch enable input (active LOW)
port B, 3-state output 7
port B, 3-state output 6
port B, 3-state output 5
port B, 3-state output 4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 20 April 2005
4 of 19
Philips Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
Pin description
…continued
Pin
19
20
21
22
23
24
Description
port B, 3-state output 3
port B, 3-state output 2
port B, 3-state output 1
port B, 3-state output 0
B-to-A enable input (active LOW)
supply voltage
Table 3:
Symbol
B3
B2
B1
B0
EBA
V
CC
7. Functional description
7.1 Function table
Table 4:
Status
Disabled
Disabled + latch
Latch + display
Transparent
Hold
[1]
Function table
[1]
Control
OExx
H
X
L
L
L
L
Exx
X
H
↑
L
L
L
LExx
X
X
L
↑
L
H
Input
An or Bn
X
X
h
l
h
l
H
L
X
Output
An or Bn
Z
Z
Z
Z
L
H
L
H
NC
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑
= LOW-to-HIGH clock transition;
NC = no change;
Z = high-impedance OFF-state.
9397 750 14756
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 20 April 2005
5 of 19
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