November 2003
rev 1.0
DDR 24-Bit to 48-Bit Registered Buffer
ASM4SSTVF32852
Features
•
•
•
•
•
Differential clock signals.
Supports SSTL_2 class II specifications on inputs
and outputs.
Low voltage operation.
•
V
DD
= 2.3V to 2.7V.
Available in 114 ball BGA package.
Industrial temperature range also available.
To ensure that outputs are at a defined logic state
before a stable clock has been supplied, RESETB must
be held at a logic “Low” level during power-up.
In the DDR DIMM application, RESETB is specified to
be asynchronous with respect to CLK/CLKB. Therefore,
no timing relationship can be guaranteed between the
two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be
driven to a logic “Low” level quickly relative to the time
to disable the differential input receivers. This ensures
there are no “glitches” on any output. However, when
coming out of low power standby state, the register will
become active quickly relative to the time taken to
enable the differential input receivers. When the data
inputs are at a logic level “Low” and the clock is stable
during the “Low-to-High” transition of RESETB until the
input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal
bus driver designed for 2.3V to 2.7V V
DD
operation and
SSTL_2 I/O levels except for the LVCMOS RESETB
input.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow,
and CLKB is used to maintain sufficient noise margins,
whereas the RESETB, an LVCMOS asynchronous
signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby
mode of operation.
A logic “Low” level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic “Low” state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Please note that RESETB must always be
supported with a LVCMOS levels at a valid logic state
since VREF may not be stable during power-up.
Applications
•
•
DDR Memory Modules.
Provides complete DDR DIMM logic solution with
ASM5CVF857, ASM4SSTVF16857 and
ASM4SSTVF16859.
•
SSTL_2 compatible data registers.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.0
Block Diagram
CLK
CLKB
ASM4SSTVF32852
RESETB
R
CLK
Q1A
D1
VREF
D1
Q1B
To 23 Other Channels
Pin Configurations
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
2
3
4
5
6
114-Pin Ball BGA
DDR 24-Bit to 48-Bit Registered Buffer
2 of 13
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.0
ASM4SSTVF32852
Pin Descriptions
Pin #
R1, P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1,
G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2
R6, P6, N6, M5,M6, L5, L6, K6, K5, J5, J6, H6,
G6, G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5
E2, B3, D3, G3, J3, L3, M3, P3, B4,
D4, G4, J4, L4, M4, P4, E5
B2, M2, P2, C3, E3, F3, H3, K3,
N3, C4, E4, F4, H4, K4, N4, B5, M5, P5
W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5,
W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2
A3
A4
H2, H5, R2, R5
R3
R4
Pin Name
Type
Description
Q (24:1)A
O
Data output.
Q (24:1)A
O
Data output.
GND
P
Ground.
VDDQ
P
Output supply voltage, 2,5V nominal.
D(24:1)
CLK
CLKB
VDD
RESETB
VREF
I
I
I
P
I
I
Data input.
Positive master clock input.
Negative master clock input.
Core supply voltage, 2.5V nominal.
Reset (Active Low).
Input reference, 1.25V nominal.
DDR 24-Bit to 48-Bit Registered Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.0
Pin Configuration Assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Q2A
Q3A
Q5A
Q7A
Q8A
Q10A
Q12A
Q13A
Q14A
Q17A
Q18A
Q20A
Q22A
Q23A
Q24A
D2
D4
D5
D8
2
Q1A
VDDQ
Q4A
Q6A
GND
Q9A
Q11A
VDD
Q15A
Q16A
Q19A
VDDQ
Q21A
VDDQ
VDD
D1
D3
D7
D9
3
CLK
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
RESETB
D6
D10
D11
D12
4
CLKB
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
VREF
D18
D22
D23
D24
5
Q1B
VDDQ
Q4B
Q6B
GND
Q9B
Q11B
VDD
Q15B
Q16B
Q19B
VDDQ
Q21B
VDDQ
VDD
D13
D15
D19
D21
ASM4SSTVF32852
6
Q2B
Q3B
Q5B
Q7B
Q8B
Q10B
Q12B
Q13B
Q14B
Q17B
Q18B
Q20B
Q22B
Q23B
Q24B
D14
D16
D17
D20
DDR 24-Bit to 48-Bit Registered Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.0
Truth Table
1
Inputs
RESET#
L
H
H
H
CLK
X or floating
↑
↑
L or H
CLK#
X or floating
↓
↓
L or H
D
X or floating
H
L
X
ASM4SSTVF32852
Q Outputs
Q
L
H
L
Q
02
Note:
1. H=High signal level, L=Low signal level,
↑
= transition from low to high,
↓
= transition from high to low, X = don’t care
2. Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Input Voltage
1
Output Voltage
1,2
Input Clamp Current
Output Clamp Current
Continuous Output Current
VDD, VDDQ or GND current/pin
Package Thermal Impedance
3
Min
-65
-0.5
-0.5
-0.5
± 50
±50
±50
100
55
Max
+150
3.6
V
DD
+ 0.5
V
DD
+ 0.5
Unit
°C
V
V
V
mA
mA
mA
mA
°C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
0
> V
DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
DDR 24-Bit to 48-Bit Registered Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
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