Micrel, Inc.
Precision Edge
ULTRA PRECISION DUAL 2:1 CML
SY58025U
MUX WITH INTERNAL I/O TERMINATION
Precision Edge
®
SY58025U
®
FEATURES
Two independent differential 2:1 multiplexers
Guaranteed AC performance over temperature and
voltage:
• DC-to >10.7Gbps data rate throughput
• <290ps IN-to-Out t
pd
• <70ps t
r
/ t
f
times
Unique, patent-pending input isolation design
minimizes crosstalk
Ultra-low jitter design:
• <1ps
RMS
random jitter
• <10ps
PP
deterministic jitter
• <10ps
PP
total jitter (clock)
• <0.7ps
RMS
crosstalk-induced jitter
Unique, patent-pending 50½ input termination and
VT pin accepts DC-coupled and AC-coupled inputs
(CML, LVDS, PECL)
Typical 400mV CML output swing (R
L
= 50½)
Internal 50½ input termination
Power supply 2.5V ±5% or 3.3V ±10%
–40°C to +85°C temperature range
Available in 32-pin (5mm
∞
5mm) MLF
®
package
Precision Edge
®
DESCRIPTION
The SY58025U features two ultra-fast, low jitter 2:1
differential muxes with a guaranteed maximum data or clock
throughput of 10.7Gbps or 7GHz, respectively.
The SY58025U differential inputs include a unique,
internal termination design that allows access to the
termination network through a VT pin. The device easily
interfaces to different logic standards, both AC- and DC-
coupled, without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution. The differential CML output is optimized for 50½
environments with internal 50½ source termination and a
400mV output swing.
The SY58025U operates from a 2.5V or 3.3V supply and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY58025U is part of Micrel’s Precision
Edge
®
product family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
APPLICATIONS
Data communication systems
All SONET OC3-OC-768 applications
All Fibre Channel applications
All GigE applications
FUNCTIONAL BLOCK DIAGRAM
INA0
50Ω
V
TA0
50Ω
/INA0
V
REF-ACA0
INA1
50Ω
V
TA1
50Ω
/INA1
V
REF-ACA1
SELA
(TTL/CMOS)
1
S
MUX A
0
INB0
50Ω
V
TB0
50Ω
0
QA
/QA
/INB0
V
REF-ACB0
INB1
50Ω
V
TB1
50Ω
/INB1
V
REF-ACB1
SELB
(TTL/CMOS)
1
S
MUX B
QB
/QB
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
MicroLeadFrame
and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: August 2007
Micrel, Inc.
Precision Edge
®
SY58025U
PACKAGE/ORDERING INFORMATION
INA1
VREF-ACA1
VTA1
INA1
/INA0
VREF-ACA0
VTA0
INA0
Ordering Information
(1)
Part Number
24
23
22
21
20
19
18
17
Package
Type
MLF-32
MLF-32
MLF-32
MLF-32
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY58025U
SY58025U
SY58025Uwith
Pb-Free bar-line indicator
SY58025U with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
32 31 30 29 28 27 26 25
INB0
VTB0
VREF-ACB0
/INB0
INB1
VTB1
VREF-ACB1
/INB1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
VCC
QA
/QA
VCC
NC
SELA
VCC
SY58025UMI
SY58025UMITR
(2)
SY58025UMG
(3)
SY58025UMGTR
(2, 3)
32-Pin MLF
®
(MLF-32)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number
25, 28,
29, 32,
1, 4,
5, 8
Pin Name
INA0, /INA0,
INA1, /INA1,
INB0, /INB0,
INB1, /INB1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair
internally terminates to a V
T
pin through 50½. Note that these inputs will default to an
indeterminate state if left open. Unused differential input pairs can be terminated by
connecting one input to V
CC
and the complementary input to GND through a 1k½ resistor.
The VT pin is to be left open in this configuration. Please refer to the “Input Interface
Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
pin. Each V
T
pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs
select the inputs to the multiplexers. These inputs are internally connected to a 25k½
pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold
is V
CC
/2.
Reference Output Voltage: These outputs bias to V
CC
–1.2V. Connect to the VT pin when
AC-coupling the data inputs. Bypass with 0.01µF low ESR capacitor to V
CC
. Maximum
current source or sink is 0.5mA. See “Input Interface Applications” section.
Positive Power Supply: Bypass with 0.1µF™ℑ0.01µF low ESR capacitors.
Differential CML Outputs: MUX A and MUX B selected CML outputs. See “Output
Interface Applications” section for termination. Refer to the “Truth Table” for logic
operation.
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Not connected.
26, 30, 2, 6
18, 15
27, 31, 3, 7
10, 13, 16,
17, 20, 23
22, 21,
12, 11
9, 24
14, 19
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
GND
VCC
/QB
QB
VCC
NC
SELB
VCC
VTA0 , VTA1,
VTB0, VTB1
SELA, SELB
VREF-ACA0,
VREF-ACA1,
VREF-ACB0,
VREF-ACB1
VCC
QA, /QA,
QB, /QB
GND,
Exposed pad
NC
2
Micrel, Inc.
Precision Edge
®
SY58025U
Absolute Maximum Ratings
(1)
Power Supply Voltage (V
CC
) ...................... –0.5V to +4.0V
Input Voltage (V
IN
) .......................................... –0.5V to V
CC
CML Output Voltage (V
OUT
) ........... V
CC
–1.0V to V
CC
+0.5V
Termination Current
(3)
Source or sink current on V
T
pin......................... ±100mA
Input Current
Source or sink current on IN, /IN pin .................... ±50mA
Current (V
REF-AC
)
Source or sink current on V
REF-AC(3)
................... ±1.5mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature Range (T
S
) ........... –65°C to +150°C
Operating Ratings
(2)
Power Supply Voltage (V
CC
) ............... +2.375V to +2.625V
............................................................. +3.0V to +3.6V
Ambient Temperature Range (T
A
) .............. –40°C to +85°C
Package Thermal Resistance
(4)
MLF
®
(θ
JA
)
Still-Air ............................................................. 35°C/W
MLF
®
(ψ
JB
)
Junction-to-board ............................................ 20°C/W
DC ELECTRICAL CHARACTERISTICS
(5)
T
A
= –40°C to +85°C; unless otherwise stated.
Symbol
V
CC
I
CC
R
DIFF_IN
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
T IN
V
REF-AC
Notes:
1. Permanent device damage may occur if the ratings in “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional
operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability, use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB.
Ψ
JB
uses 4-
layer
θ
JA
in still air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50½ pull-ups. See Figure 1b.
7. V
IH
(min) not lower than 1.2V.
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input Resistance
(IN-to-V
T
, /IN-to-V
T
)
Input High Voltage (IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing (IN, /IN)
Differential Input Voltage Swing
|IN - /IN|
In to V
T
(IN, /IN)
Output Reference Voltage
Condition
V
CC
= 2.5V
V
CC
= 3.3V
No load, max. V
CC
.
(6)
Min
2.375
3.0
Typ
2.5
3.3
115
Max
2.625
3.6
140
120
60
V
CC
V
IH
–0.1
1.7
Units
V
V
mA
½
½
V
V
V
V
80
40
Note 7
V
CC
–1.6
0
See Figure 1a.
See Figure 1b.
0.1
0.2
100
50
1.28
V
CC
–1.3 V
CC
–1.2 V
CC
–1.1
V
V
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY58025U
CML OUTPUT DC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to +85°C; R
L
= 100½ across each output pair, or equivalent, unless otherwise stated.
Symbol
V
OH
V
OUT
V
DIFF-OUT
R
OUT
Parameter
Output High Voltage
Q, /Q
Output Voltage Swing
Q, /Q
Differential Output Voltage Swing
Q, /Q
Output Source Impedance
Q, /Q
See Figure 1a.
See Figure 1b.
Condition
Min
V
CC
–0.020
325
650
40
400
800
50
60
Typ
Max
V
CC
Units
V
mV
mV
½
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to 85°C unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
–125
–300
Condition
Min
2.0
0.8
50
Typ
Max
Units
V
V
µA
µA
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY58025U
AC ELECTRICAL CHARACTERISTICS
(8)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to +85°C; R
L
= 100½ across each output pair, or equivalent, unless otherwise stated.
Symbol
f
MAX
t
pd
Parameter
Maximum Operating Frequency
V
OUT
ž 200mV
Propagation Delay
IN-to-Q
SEL-to-Q
t
SKEW
Input-to-Input Skew (Within-Bank)
Bank-to-Bank Skew
Part-to-Part Skew
t
JITTER
Data
Clock
Random Jitter (RJ)
Deterministic Jitter (DJ)
Cycle-to-Cycle Jitter
Total Jitter (TJ)
Crosstalk-Induced Jitter
Channel-to-Channel
t
r
, t
f
Notes:
8. High-speed AC parameters are guaranteed by design and characterization. V
IN
swing ž 100mV unless otherwise noted.
9. Input-to-input skew is the difference in time between two inputs to the output within a bank.
10. Bank-to-bank skew is the difference in time from input to the output between bank.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
12. Random jitter is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps/3.2Gbps.
13. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
23
–1 PRBS pattern
14. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
–T
n–1
where T is the time between rising edges of the output
signal.
15. Total jitter definition: with an ideal clock input of frequency - f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
16. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
Condition
NRZ Data
Clock
Min
10.7
Typ
Max
Units
Gbps
6
140
100
290
400
3
5
15
20
100
1
10
1
10
0.7
20
50
70
GHz
ps
ps
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
ps
RMS
ps
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
Note 15
Note 16,
Within-bank.
At full swing.
Output Rise/Fall Time 20% to 80%
TRUTH TABLES
INA0
0
1
X
X
INB0
0
1
X
X
/INA0
1
0
X
X
/INB0
1
0
X
X
INA1
X
X
0
1
INB1
X
X
0
1
/INA1
X
X
1
0
/INB1
X
X
1
0
SELA
0
0
1
1
SELB
0
0
1
1
QA
0
1
0
1
QB
0
1
0
1
/QA
1
0
1
0
/QB
1
0
1
0
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
