DSP56F802/D
Rev. 4.0, 08/2003
56F802
Technical Data
56F802 16-bit Hybrid Controller
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Up to 30 MIPS operation at 60MHz core
frequency
Up to 40 MIPS operation at 80MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
Hardware DO and REP loops
6-channel PWM Module with fault input
Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
Serial Communications Interface (SCI)
6
PWM Outputs
Fault A0
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8K
×
16-bit words Program Flash
1K
×
16-bit words Program RAM
2K
×
16-bit words Data Flash
1K
×
16-bit words Data RAM
2K
×
16-bit words Boot Flash
Two General Purpose Quad Timers with 2
external outputs
JTAG/OnCE
TM
port for debugging
4 shared GPIO
On-chip relaxation oscillator
32-pin LQFP Package
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PWMA
RESET
5
JTAG/
OnCE
Port
VCAPC V
DD
2
2
3
Digital Reg
Analog Reg
V
SS
* V
DDA
V
SSA
2
3
A/D1
A/D2
VREF
ADC
Interrupt
Controller
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
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PAB
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PDB
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IPBB
CONTROLS
16
Relaxation
Oscillator
PLL
2
XDB2
CGDB
XAB1
XAB2
.
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2
SCI0
or
GPIO
INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
16-Bit
56800
Core
Application-
Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
*
includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F802 Block Diagram
© Motorola, Inc., 2003. All rights reserved.
Part 1 Overview
1.1 56F802 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
Single-cycle 16
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16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low-cost, high-volume Flash solution
— 8K
×
16 bit words of Program Flash
— 1K
×
16-bit words of Program RAM
— 2K
×
16-bit words of Data Flash
— 1K
×
16-bit words of Data RAM
— 2K
×
16-bit words of Boot Flash
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Programmable Boot Flash supports customized boot code and field upgrades of stored code through
a variety of interfaces (JTAG)
1.1.3
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Peripheral Circuits for 56F802
Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;
supports both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support
two simultaneous conversions; ADC and PWM modules can be synchronized
Two General Purpose Quad Timers with two external pins (or two GPIO)
Serial Communication Interface (SCI) with two pins (or two GPIO)
Four multiplexed General Purpose I/O (GPIO) pins
2
56F802 Technical Data
MOTOROLA
56F802 Description
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Computer-Operating Properly (COP) watchdog timer
External interrupts via GPIO
Trimmable on-chip relaxation oscillator
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
Integrated power supervisor
1.2 56F802 Description
The 56F802 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,
and compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words
of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0%
MOTOROLA
56F802 Technical Data
3
to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC
Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and
Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection with sufficient
output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection
feature for key parameters is also included. The PWM is double-buffered and includes interrupt control to
permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output
to synchronize the Analog-to-Digital Converters.
The 56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels. A
full set of standard programmable peripherals is provided that include a Serial Communications Interface
(SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO)
if that function is not required. An on-chip relaxation oscillator eliminates the need for an external crystal.
1.3 State of the Art Development Environment
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Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-
use component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in
Table 1
are required for a complete description and proper design with the
56F802. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at
www.motorola.com/semiconductors.
Table 1. 56F802 Chip Documentation
Topic
DSP56800
Family Manual
DSP56F801/803/805/807
User’s Manual
56F802
Technical Data Sheet
56F802
Product Brief
Description
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F802, 56F803, 56F805, and 56F807
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
Summary description and block diagram of the 56F802
core, memory, peripherals and interfaces
Order Number
DSP56800FM/D
DSP56F801-7UM/D
DSP56F802/D
DSP56F802PB/D
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56F802 Technical Data
MOTOROLA
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Signal/Symbol
PIN
PIN
PIN
PIN
1.
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
1
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
“asserted”
“deasserted”
Examples:
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications
MOTOROLA
56F802 Technical Data
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