STK17TA8
128k X 8 AutoStore nvSRAM with
Real Time Clock
Features
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Description
The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM
(nvSRAM) with a full featured real time clock in a reliable,
monolithic integrated circuit.
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
nvSRAM Combined with Integrated Real Time Clock Functions
(RTC, Watchdog Timer, Clock Alarm, Power Monitor)
Capacitor or Battery Backup for RTC
25, 45 ns Read Access and Read/Write Cycle Time
Unlimited Read/Write Endurance
Automatic nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year nonvolatile Data Retention
Single 3 V +20%, -10% Power Supply
Commercial and Industrial Temperatures
48-pin 300-mil SSOP Package (RoHS-Compliant)
en
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Logic Block Diagram
fo
rN
ew
D
V
CC
ec
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
Quantum Trap
1024 X 1024
STORE
RECALL
ROW DECODER
m
om
STATIC RAM
ARRAY
1024 X 1024
es
i
V
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
RTC
MUX
gn
V
RTCbat
V
RTCcap
SOFTWARE
DETECT
s
HSB
A
15
– A
0
R
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
X
1
X
2
INT
A
16
– A
0
G
E
W
N
ot
A
0
A
1
A
2
A
3
A
4
A
10
A
11
Cypress Semiconductor Corporation
Document #: 001-52039 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 25, 2009
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STK17TA8
Contents
Features ................................................................................1
Description ...........................................................................1
Logic Block Diagram ...........................................................1
Contents ...............................................................................2
Pinouts .................................................................................3
Pin Descriptions ..................................................................3
Absolute Maximum Ratings ...............................................4
RF (SSOP-48) Package Thermal
Characteristics ................................................................ 4
DC Electrical Characteristics .............................................4
AC Test Conditions .............................................................5
Capacitance .........................................................................5
RTC DC Characteristics ......................................................6
SRAM READ Cycles #1 and #2 ...........................................7
SRAM WRITE Cycles #1 and #2 .........................................8
AutoStore/Power Up Recall ................................................9
Software-Controlled STORE/RECALL Cycle ...................10
Hardware STORE Cycle ....................................................11
Soft Sequence Commands ...............................................11
MODE Selection .................................................................12
nvSRAM Operation ............................................................13
SRAM READ ................................................................ 13
SRAM WRITE .............................................................. 13
AutoStore Operation..................................................... 13
Hardware STORE (HSB) Operation............................. 13
Hardware RECALL (POWER UP)................................ 13
Software STORE...........................................................13
Software RECALL ........................................................ 14
Data Protection............................................................. 14
Noise Considerations ................................................... 14
Preventing AutoStore ................................................... 14
Best Practices .............................................................. 14
Low Average Active Power ...........................................14
RTC Operations .................................................................15
Real Time Clock ........................................................... 15
Reading The Clock....................................................... 15
Setting The Clock ..........................................................15
Backup Power .............................................................. 15
Stopping And Starting The RTC Oscillator................... 15
Calibrating The Clock ................................................... 16
Alarm .............................................................................16
Watchdog Timer ........................................................... 16
Power Monitor .............................................................. 16
Interrupts ...................................................................... 17
Interrupt Register.......................................................... 17
Flags Register .............................................................. 17
RTC Register ......................................................................18
Register Map Detail ...........................................................19
Ordering Information .........................................................22
STK17TA8-R F 45 ITR ........................................................22
Ordering Codes .................................................................22
Package Diagrams .............................................................23
Document History Page ....................................................24
Sales, Solutions, and Legal Information .........................24
Worldwide Sales and Design Support.......................... 24
Products ....................................................................... 24
Document #: 001-52039 Rev. *A
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STK17TA8
Pinouts
Figure 1. Pin Diagram - 48-PIn SSOP
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
INT
A
4
NC
NC
NC
V
SS
NC
V
RTCbat
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
X
1
X
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
W
A
13
A
8
A
9
NC
Relative PCB Area Usage
[1]
(TOP)
NC
NC
V
SS
NC
V
RTCcap
DQ
6
G
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
Pin Name
A
16
-A
0
DQ
7
-DQ
0
E
W
G
X
1
X
2
V
RTCcap
V
RTCbat
V
CC
HSB
I/O Type
Input
I/O
Input
Input
Input
Output
Input
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Pin Descriptions
Address:
The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes
in the clock register map
Data:
Bi-directional 8-bit data bus for accessing the nvSRAM and RTC
Chip Enable:
The active low E input selects the device
N
Power Supply
Battery supplied backup RTC supply voltage (Left unconnected if V
RTCcap
is used)
Power Supply
Power:
3.0V, +20%, -10%
I/O
Hardware Store Busy:
When low this output indicates a Store is in progress. When pulled low external
to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not
connected. (Connection Optional).
Interrupt Control:
Can be programmed to respond to the clock alarm, the watchdog timer and the
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
INT
V
CAP
V
SS
NC
Power Supply
Autostore Capacitor:
Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Power Supply
Ground
No Connect
Unlabeled pins have no internal connections.
Note
1. For detailed package size specifications, See
“Package Diagrams”
on page 23..
Document #: 001-52039 Rev. *A
ot
Power Supply
Capacitor supplied backup RTC supply voltage (Left unconnected if V
RTCbat
is used)
Output
R
ec
Output Enable:
The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tristate.
Crystal Connection, drives crystal on startup
Crystal Connection for 32.768 kHz crystal
om
Write Enable:
The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E
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Description
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STK17TA8
Absolute Maximum Ratings
Voltage on Input Relative to Ground ................–0.1V to 4.1V
Voltage on Input Relative to V
SS
.........–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB.....................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature ................................... –55°C to 140°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
Note
Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliablity.
RF (SSOP-48) Package Thermal Characteristics
θ
jc
6.2 C/W;
θ
ja
51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm]
DC Electrical Characteristics
(V
CC
= 2.7V-3.6V)
Symbol
I
CC1
Parameter
Average V
CC
Current
Commercial
Min
Max
65
50
Industrial
Min
Max
70
55
D
ew
Units
mA
mA
Notes
t
AVAV
= 25 ns
t
AVAV
= 45 ns
Dependent on output loading and
cycle rate. Values obtained
without output loads.
All Inputs Don’t Care, V
CC
= max
Average current for duration of
STORE
cycle (t
STORE
)
W
≥
(V
CC
– 0.2V)
All Other Inputs Cycling at CMOS
Levels
Dependent on output loading and
cycle rate. Values obtained
without output loads.
All Inputs Don’t Care
Average current for duration of
STORE cycle (t
STORE
)
E
≥ (V
CC
-0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
-0.2V)
Standby current level after
nonvolatile cycle complete
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 2 mA (except HSB)
I
OUT
= 4 mA
I
CC3
I
CC4
I
SB
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
Note
■
■
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
N
ot
R
V
CC
Standby Current
(Standby, Stable CMOS Levels)
ec
Average V
CAP
Current during
<Emphasis>AutoStore™ Cycle
om
m
Average V
CC
Current at t
AVAV
=
200ns
3V, 25°C, Typical
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I
CC2
Average V
CC
Current during
STORE
3
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3
10
10
3
3
3
3
±1
±1
±1
±1
2.0
V
CC
+ 0.5
2.0
V
CC
+ 0.5
V
SS
–0.5
0.8
V
SS
–0.5
0.8
2.4
2.4
0.4
0.4
The HSB pin has I
OUT
=-10uA for V
OH
of 2.4V, this parameter is characterized but not tested.
The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.
Document #: 001-52039 Rev. *A
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mA
mA
mA
mA
mA
mA
V
V
V
V
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DC Output Current (1 output at a time, 1s duration).... 15 mA
STK17TA8
DC Electrical Characteristics
(continued)
(V
CC
= 2.7V-3.6V)
Symbol
T
A
V
CC
V
CAP
NV
C
DATA
R
Parameter
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE operations
Data Retention
Commercial
Min
Max
0
70
2.7
3.6
17
57
200
20
Industrial
Min
Max
– 40
85
2.7
3.6
17
57
200
20
Units
°C
V
μF
Notes
3.0V +20%, -10%
Between V
CAP
pin and V
SS
, 5V
rated.
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load..................................See
Figure 2
and
Figure 3
(T
A
= 25°C, f = 1.0MHz)
[2]
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
fo
Max
7
7
rN
Units
pF
pF
Capacitance
ew
Conditions
ΔV
= 0 to 3V
ΔV
= 0 to 3V
3.0V
577 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
3.0V
577 Ohms
5 pF
INCLUDING
SCOPE AND
FIXTURE
om
m
OUTPUT
789 Ohms
N
ot
Figure 3. AC Output Loading for Tristate Specs
(t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
R
ec
OUTPUT
789 Ohms
Note
2. These parameters are guaranteed but not tested.
Document #: 001-52039 Rev. *A
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Figure 2. AC Output Loading
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AC Test Conditions
gn
K
Years At 55
°C
s
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