SN74LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate
in either a synchronous parallel load or a serial shift-right mode, as
determined by the Select input. An asynchronous active LOW Master Reset
(MR) input overrides the synchronous operations and clears the register. An
active HIGH Output Enable (OE) input controls the 3-state output buffers, but
does not interfere with the other operations. The fourth stage also has a
conventional output for linking purposes in multi-stage serial operations.
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
•
Shift Left or Parallel 4-Bit Register
•
3-State Outputs
•
Input Clamp Diodes Limit High-Speed Termination Effects
J SUFFIX
CERAMIC
CASE 620-09
16
1
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
O0
15
O1
14
O2
13
O3
12
Q3
11
CP
10
OE
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
1
MR
2
DS
3
P0
4
P1
5
P2
6
P3
7
S
8
GND
16
1
D SUFFIX
SOIC
CASE 751B-03
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
5 U.L.
P0 – P3
DS
S
CP
MR
OE
O0 – O3
Q3
Parallel Inputs
Serial Data Input
Mode Select Input
Clock (Active LOW) Input
Master Reset (Active LOW) Input
Output Enable (Active HIGH) Input
3-State Register Outputs
Register Output
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
10 U.L.
ORDERING INFORMATION
SN74LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
7 3
4
5
6
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
2
10
9
DS
CP
OE
S P0 P1 P2 P3
Q3
MR O0 O1 O2 O3
11
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-551
SN74LS395
LOGIC DIAGRAM
S
Ds
P0
P1
P2
P3
CP
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CD
MR
CD
CD
CD
OE
O0
O1
O2
O3
Q3
FUNCTION DESCRIPTION
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
Parallel (Pn) input or from the preceding stage. When the
Select input is HIGH, the Pn inputs are enabled. A LOW signal
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
S input is LOW, a CP HIGH-LOW transition transfers data in
Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished
by connecting the outputs back to the Pn inputs, but offset one
place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q0 – Q3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still be
accomplished, however.
MODE SELECT — TRUTH TABLE
Inputs @ tn
Operating Mode
Asynchronous Reset
Shift, SET First Stage
Shift, RESET First Stage
Parallel Load
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
tn, n + 1 = time before and after CP HIGH-to-LOW transition
NOTE:
When OE is HIGH, outputs O0 – O3 are in the high impedance state; however, this does not affect other operations or the Q3 output.
Outputs @ tn+1
Ds
X
H
L
X
Pn
X
X
X
Pn
O0
L
H
L
P0
O1
L
O0n
O0n
P1
O2
L
O1n
O1n
P2
O3
L
O2n
O2n
P3
MR
L
H
H
H
CP
X
S
X
L
L
H
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
FAST AND LS TTL DATA
5-552
SN74LS395
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
VOL
IOZH
IOZL
IIH
IIL
IOS
Output LOW Voltage
0.35
Output Off Current HIGH
Output Off Current LOW
Input HIGH Current
– 0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
Total, Output HIGH
ICC
Total, Output LOW
34
mA
– 20
– 0.4
– 100
31
0.5
20
– 20
20
V
µA
µA
µA
mA
mA
mA
mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VO = 2.4 V
VCC = MAX, VO = 0.4 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX, OE = GND, CP = GND
VCC = MAX, OE = 4.5 V, CP
momentary 3.0 V then GND
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
fMAX
tPHL
tPLH
tPHL
tPZH
tPZL
tPLZ
tPHZ
Parameter
Maximum Input Clock Frequency
Propagation Delay, Clear to Output
Propagation Delay, Low to High
Propagation Delay, High to Low
Output Enable Time
Output Disable Time
Min
30
Typ
45
22
15
25
15
17
12
11
35
30
30
25
25
20
17
Max
Unit
MHz
ns
ns
ns
ns
CL = 5.0 pF
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
ts
ts
th
Parameter
Clock Pulse Width
Setup Time, Mode Select
Setup Time, All Others
Data Hold Time
Min
16
40
20
10
Typ
Max
Unit
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
FAST AND LS TTL DATA
5-553
SN74LS395
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
D
*
1.3 V
1.3 V
LOAD SERIAL DATA
SHIFT RIGHT
th(H)
S
1.3 V
ts(L)
th(L)
LOAD PARALLEL DATA
1.3 V
ts(H)
CP OR
MR
1.3 V
tW
tPHL
1/fmax
1.3 V
ts(L)
tPLH
CP
1.3 V
th(L)
ts(H)
th(H)
Q
1.3 V
*The Data Input is DS for S = LOW and Pn for S = HIGH.
Figure 1
Figure 2
VE
1.3 V
1.3 V
VE
tPLZ
1.3 V
tPZH
1.3V
tPHZ
tPZL
VOUT
1.3 V
≈
1.3 V
VOL
0.5 V
VOUT
1.3 V
≥
VOH
≈
1.3 V
0.5 V
Figure 3
Figure 4
AC LOAD CIRCUIT
VCC
RL
SWITCH POSITIONS
SYMBOL
SW1
Open
Closed
Closed
Closed
SW2
Closed
Open
Closed
Closed
SW1
tPZH
tPZL
TO OUTPUT
UNDER TEST
tPLZ
tPHZ
5 k
Ω
SW2
CL*
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-554
-A-
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4.
MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5.
751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
16
9
-B-
1
8
P
8 PL
0.25 (0.010)
M
B
M
R X 45°
G
-T-
D
16 PL
0.25 (0.010)
M
C
SEATING
PLANE
K
T
B
S
M
F
J
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
3.80
1.35
0.35
0.40
10.00
4.00
1.75
0.49
1.25
INCHES
MIN
MAX
0.386
0.150
0.054
0.014
0.016
0.393
0.157
0.068
0.019
0.049
1.27 BSC
0.19
0.10
0
0.25
0.25
7
0.050 BSC
0.008
0.004
0
0.009
0.009
7
°
°
°
°
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
9
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: INCH.
DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4.
DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5.
6.
ROUNDED CORNERS OPTIONAL.
648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
B
1
8
F
S
C
-T-
K
SEATING
PLANE
L
H
G
D
16 PL
0.25 (0.010)
M
J
M
T
A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MILLIMETERS
MIN
MAX
18.80
6.35
3.69
0.39
1.02
19.55
6.85
4.44
0.53
1.77
INCHES
MIN
MAX
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.070
2.54 BSC
1.27 BSC
0.21
2.80
7.50
0
0.38
3.30
7.74
10
0.100 BSC
0.050 BSC
0.008
0.110
0.295
0
0.015
0.130
0.305
10
°
°
°
°
0.51
1.01
0.020
0.040
-A-
16
9
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B-
1
8
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
C
L
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-T-
SEATING
PLANE
K
E
F
D
16 PL
0.25 (0.010)
M
N
G
T
A
S
M
J
16 PL
0.25 (0.010)
M
T
B
S
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
19.05
6.10
19.55
7.36
4.19
0.39
0.53
INCHES
MIN
MAX
0.750
0.240
0.770
0.290
0.165
0.015
0.021
1.27 BSC
1.40
1.77
0.050 BSC
0.055
0.070
2.54 BSC
0.23
0.27
5.08
7.62 BSC
0
0.100 BSC
0.009
0.011
0.200
0.300 BSC
0
°
15
°
°
15
°
0.39
0.88
0.015
0.035
FAST AND LS TTL DATA
5-555
嵌入式系统
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