The ASM2I2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has
10 outputs, 8 of which can be used to drive up to four
SDRAM SO-DIMMs, and the remaining can be used for
external feedback to a PLL. The device operates at 3.3V
and outputs can run up to 133MHz, thus making it
compatible with Pentium II
®
processors.
The ASM2I2310ANZ also includes a serial interface (IIC),
which can enable or disable each output clock. The IIC is
Slave Receiver only and is Standard mode compliant. IIC
Master can write into the IIC registers but cannot read
back. The first two bytes after address should be ignored
by IIC Block and data is valid after these two bytes as given
in IIC Byte Flow Table. On power-up, all output clocks are
enabled. A separate Output Enable pin facilitates testing on
ATE.
i
i
Pentium II is a registered trademark of Intel Corporation
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDATA
Serial Interface
Decoding
SCLOCK
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
OE
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.4
Pin Configuration
28 Pin SSOP Package-- Top View
ASM2I2310ANZ
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
V
DD
SDRAM8
V
SS
V
DDIICC
SDATA
1
2
3
4
5
6
7
28
27
26
25
24
23
22
V
DD
SDRAM7
SDRAM6
V
SS
V
DD
SDRAM5
SDRAM4
V
SS
OE
V
DD
SDRAM9
V
SS
V
SSIIC
SCLOCK
ASM2I2310ANZ
8
9
10
11
12
13
14
21
20
19
18
17
16
15
Pin Description
Pins
1, 5, 10, 19, 24, 28
4, 8, 12, 17, 21, 25
13
16
9
20
14
15
2, 3, 6, 7
22, 23, 26, 27
11, 18
V
DD
V
SS
V
DDIIC
V
SSIIC
BUF_IN
OE
SDATA
SCLK
SDRAM [0–3]
SDRAM [4–7]
SDRAM [8–9]
Name
Type
P
P
P
P
I
I
I/O
I
O
O
O
Ground
Description
3.3V Digital voltage supply
3.3V Serial interface voltage supply
Ground for serial interface
Input clock, 5V tolerant
Output Enable, three-states outputs when LOW.
Internal pull-up to V
DD
Bi-directional Serial data pin. Internal pull-up to V
DD.
5V tolerant
Serial clock input. Internal pull-up to V
DD.
5V tolerant
SDRAM byte 0 Clock Outputs
SDRAM byte 1 Clock Outputs
SDRAM byte 2 Clock Outputs
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
2 of 12
June 2005
rev 0.4
Device Functionality
OE
0
1
ASM2I2310ANZ
Byte 1: SDRAM Active/Inactive Register
1
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM [0–17]
High-Z
1 x BUF_IN
Pin #
27
26
23
22
--
--
--
--
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Unused
Unused
Unused
Unused
Serial Configuration Map
•
The Serial bits will be read by the clock driver in the
following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
•
Reserved and unused bits can be programmed to either
“0” or “1”.
•
Serial interface address for the ASM2I2310ANZ is:
Byte 2: SDRAM Active/Inactive Register
1
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Pin #
18
11
--
--
--
--
--
--
Description
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 0: SDRAM Active/Inactive Register
1
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
--
--
--
--
7
6
3
2
Unused
Unused
Unused
Unused
Description
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
1
2
3
4
5
6
Description
IIC Address
Command (dummy value, ignored)
Byte Count (dummy value, ignored)
IIC Data Byte 0
IIC Data Byte 1
IIC Data Byte 2
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
3 of 12
June 2005
rev 0.4
Absolute Maximum Ratings
Symbol
V
DD
V
IN
V
INB
T
STG
T
J
T
DV
ASM2I2310ANZ
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except BUF_IN)
DC Input Voltage (BUF_IN)
Storage Temperature
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Rating
–0.5V to +7.0
–0.5V to V
DD
+ 0.5
–0.5V to +7.0
–65°C to +150
150
2000
Unit
V
V
V
°C
°C
V
Operating Conditions
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Description
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Power-up time for all V
DD
's to reach minimum specified voltage
(power ramps must be monotonic)
Min
3.135
0
20
0.05
Max
3.465
70
30
7
50
Unit
V
°C
pF
pF
ms
Electrical Characteristics
Parameter
V
IL
V
ILIIC
V
IH
V
OL
V
OH
I
CC
I
OZ
I
OFF
∆I
CC
I
i
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DDS
Description
Input LOW Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
1
Output HIGH Voltage
1
Quiescent Supply
Current
High Impedance
Output Current
OffState Current
(for SCL ,SDATA)
Change in Supply
Current
Input Leakage
Supply Current
1
Supply Current
1
Supply Current
1
Supply Current
1
Supply Current
1
Supply Current
1
Supply Current
Test Conditions
Except serial interface pins
For serial interface pins only
Min
2.0
Typ
Max
0.8
0.7
0.4
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
I
OL
= 25 mA
I
OH
= –36 mA
V
DD
= 3.465V, V
i
= V
DD
or GND
I
O
=0
V
DD
= 3.465V, V
i
= V
DD
or GND
V
DD
= 0V, V
i
= 0V or 5.5V
V
DD
= 3.135V to 3.465V
One Input at V
DD
-0.6, All other Inputs
at V
DD
or GND
V
DD
= 3.465V or GND
(Applicable to all Input Pins)
Unloaded outputs, 133MHz
Loaded outputs, 30pF, 133MHz
Unloaded outputs, 100MHz
Loaded outputs, 30pF,100MHz
Unloaded outputs, 66.67MHz
Loaded outputs, 30pF ,66.67MHz
BUF_IN=V
DD
or V
SS,
all other inputs at V
DD
2.4
50
100
±10
50
500
-5
+5
266
360
200
290
150
185
500
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
4 of 12
June 2005
rev 0.4
Switching Characteristics
1
Parameter
f
max
t
D
t
3
t
4
t
5
t
6
t
7
t
PLZ,
t
PHZ
t
PZL,
t
PZH
t
r
t
f
ASM2I2310ANZ
Name
Maximum Operating Frequency
Duty Cycle
2,3
= t
2
÷ t
1
Rising Edge Rate
3
Falling Edge Rate
3
Output to Output Skew
3
SDRAM Buffer LH Prop. Delay
3
SDRAM Buffer HL Prop. Delay
3
SDRAM Buffer Enable Delay
3
SDRAM Buffer Disable Delay
3
Rise Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Fall Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Test Conditions
Measured at 1.5V
Measured between 0.4V and
2.4V
Measured between 2.4V and
0.4V
All outputs equally loaded
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
C
L
= 10pF
C
L
= 400pF
C
L
= 10pF
C
L
= 400pF
Min
45.0
1
1
Typ
50.0
2
2
150
Max
133
55.0
4
4
225
3.5
3.5
5
5
250
Unit
MHz
%
V/nS
V/nS
pS
nS
nS
nS
nS
nS
nS
1
1
1
1
6
20
2.7
2.7
3
3
250
Note: 1 .All parameters specified with loaded outputs.
2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S
1
2
*
V
DD
Open
V
SS
V
DD
500Ω
V
I
PULSE
GENERATOR
R
T
D.U.T
500Ω
V
O
C
L
TEST
t
6
/t
7
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S
1
Open
2
*
V
DD
V
SS
Figure 1. Load circuit for Switching times
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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