November 2003
rev 1.1
ASM5P23SS08A
3.3V Zero Delay Buffer
be driven to FBK pin, and can be obtained from one of the
General Features
•
•
•
•
•
Zero input - output propagation delay, adjustable by
capacitive load on FBK input.
EMI reduced output with on-chip EMI reduction
capability.
Multiple configurations -
Configurations Table”.
Input frequency range : 10MHz to 133MHz
Multiple low-skew outputs.
•
•
•
•
•
•
•
•
Output-output skew less than 200 ps.
Device-device skew less than 700 ps.
Two banks of four outputs, three-stateable by two
select inputs.
Less than 200 ps cycle-to-cycle jitter (-1, -1H, -4, -5H).
Available in 16-pin SOIC and TSSOP packages.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
Refer “ASM5P23SS08A
outputs. The input-to-input propogation delay is guaranteed
to be less than 350ps, and the output-to-output skew is
guaranteed to be less than 250ps.
The ASM5P23SS08A has two banks of four outputs each,
which can be controlled by the select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23SS08A devices can accept the same
input clock and distribute it. In this case the skew between
the outputs of the two devices is guaranteed to be less than
700ps.
The
ASM5P23SS08A
is
available
in
five
different
configurations
(Refer “ASM5P23SS08A
Configurations
Table). The ASM5P23SS08A-1 is the base part, where the
output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P23SS08A-1H is
the high-drive version of the -1 and the rise and fall times
on this device are much faster.
The ASM5P23SS08A-2 allows the user to obtain 2X and
1X
frequencies
on
each
output
bank.
The
exact
configuration and output frequencies depends on which
output drives the feedback pin. The ASM5P23SS08A-3
allows the user to obtain 4X and 2X frequencies on the
outputs.
The ASM5P23SS08A-4 enables the user to obtain 2X
clocks on all outputs. Thus, the part is extremely versatile,
and can be used in a variety of applications.
The ASM5P23SS08A-5H is a high-drive version with
REF/2 on both banks.
Functional Description
ASM5P23SS08A is a versatile, spread spectrum output,
3.3V zero-delay buffer designed to distribute high-speed
clocks with EMI supression capability. It is available in a
16-pin package. The ASM5P23SS08A family incorporates
the latest advances in PLL spread spectrum techniques to
greatly reduce the peak EMI by
frequency
with
a
low
modulating the output
carrier
.
The
frequency
ASM5P23SS08A allows significant system cost savings by
reducing the number of circuit board layers and shielding
that are traditionally required to pass EMI regulations.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has negligible impact on system performance
while giving significant cost savings. Alliance offers options
with different spreading patterns with more spread and
greater EMI reduction.
The part has an on-chip PLL whick locks to an input clock
presented on the REF pin. The PLL feedback is required to
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
Block Diagram
/2
REF
ASM5P23SS08A
ASM5P23SS08A
Peak Reducing
PLL
MUX
CLKA1
CLKA2
FBK
/2
Extra Divider (-3,-4)
Extra Divider (-5H)
S2
Select Input
Decoding
S1
CLKA3
CLKA4
/2
CLKB1
CLKB2
Extra Divider (-2,-3)
CLKB3
CLKB4
Select Input Decoding for ASM5P23SS08A
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
1
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut-Down
Y
N
Y
N
ASM5P23SS08A Configurations
Device
ASM5P2308-1
ASM5P2308-1H
ASM5P2308-2
ASM5P2308-2
ASM5P2308-3
ASM5P2308-3
ASM5P2308-4
ASM5P2308-5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank B Frequency
Reference
Reference
Reference /2
Reference
Reference or Reference
2
2 X Reference
2 X Reference
Referemce /2
Note:
1. Outputs inverted on 2308-2 and 2308-3 in bypass mode, S2 = 1 and S1 =0.
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308-2.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
ASM5P23SS08A
These methods are expensive. Spread spectrum clocking
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave
is
composed
of
fundamental
frequency
and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of EMI.
Regulatory
agencies
test
electronic
equipment
by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as the
frequency increases. The standard methods of reducing
EMI are to use shielding, filtering, multi-layer-PCBs etc.
reduces the peak energy by reducing the Q factor of the
clock. This is done by slowly modulating the clock
frequency. The ASM5P23SXX uses the center modulation
spread spectrum technique in which the modulated output
frequency varies above and below the reference frequency
with a specified modulation rate. With center modulation,
the average frequency is the same as the un-modulated
frequency and there is no performance degradation.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output.
1500
REF-Input to CLKA/LKB Delay (ps)
1000
500
0
-30
-500
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the ASM5P23SS08A, the
FBK pin can be driven from any of the eight available
output pins. The output driving the FBK pin will be driving a
total load of 7 pF plus any additional load that it drives. The
relative loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output-output skew, be sure to load
outputs equally.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
Pin Configuration
REF
CLKA1
CLKA2
V
DD
ASM5P23SS08A
1
2
3
4
5
6
7
8
16
15
14
FBK
CLKA4
CLKA3
V
DD
GND
CLKB1
CLKB2
S2
ASM5P23SS08A
12
11
10
9
13
GND
CLKB4
CLKB3
S1
Pin Description for ASM5P23SS08A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
3
CLKA1
4
CLKA2
4
V
DD
GND
CLKB1
4
CLKB2
4
S2
5
S1
5
CLKB3
4
CLKB4
4
GND
V
DD
CLKA3
4
CLKA4
4
FBK
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
>2000
ASM5P23SS08A
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P23SS08A Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
6
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
ûC
pF
pF
pF
Note:
6. Applies to both Ref Clock and FBK.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
