A3984
DMOS Microstepping Driver with Translator
Features and Benefits
▪
Low RDS(ON) outputs
▪
Automatic current decay mode detection/selection
▪
Mixed and Slow current decay modes
▪
Synchronous rectification for low power dissipation
▪
Internal UVLO and thermal shutdown circuitry
▪
Crossover-current protection
Description
The A3984 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to
operate bipolar stepper motors in full-, half-, quarter-, and
sixteenth-step modes, with an output drive capacity of up to
35 V and ±2 A. The A3984 includes a fixed off-time current
regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A3984. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence
tables, high frequency control lines, or complex interfaces to
program. The A3984 interface is an ideal fit for applications
where a complex microprocessor is unavailable or is
overburdened.
The chopping control in the A3984 automatically selects
the current decay mode (Slow or Mixed). When a signal
occurs at the STEP input pin, the A3984 determines if
that step results in a higher or lower current in each of the
motor phases. If the change is to a higher current, then
the decay mode is set to Slow decay. If the change is to a
lower current, then the current decay is set to Mixed (set
Package: 24-pin TSSOP with exposed
thermal pad (suffix LP)
Not to scale
Continued on the next page…
Pin-out Diagram
CP1
CP2
VCP
VREG
MS1
MS2
RESET
ROSC
SLEEP
1
24 GND
Charge
Pump
2
3
23 ENABLE
22 OUT2B
Reg
4
5
21 VBB2
20 SENSE2
Translator
& Control Logic
6
7
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
8
9
VDD 10
STEP 11
REF 12
26184.30E
OSC
A3984
DMOS Microstepping Driver with Translator
Internal circuit protection includes: thermal shutdown with
hysteresis, undervoltage lockout (UVLO), and crossover-current
protection. Special power-on sequencing is not required.
The A3984 is supplied in a low-profile (1.2 mm maximum),
24-pin TSSOP with exposed thermal pad (package
LP).
It is lead
(Pb) free, with 100% matte tin leadframe plating.
Description (continued)
initially to a fast decay for a period amounting to 31.25% of
the fixed off-time, then to a slow decay for the remainder of the
off-time). This current decay control scheme results in reduced
audible motor noise, increased step accuracy, and reduced power
dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Selection Guide
Part Number
A3984SLPTR-T
Packing
4000 pieces per 13-in. reel
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current
Logic Input Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
Symbol
V
BB
I
OUT
V
IN
V
SENSE
V
REF
T
A
T
J
(max)
T
stg
Range S
Notes
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction tem-
perature of 150°C.
Rating
35
±2
–0.3 to 7
0.5
4
–20 to 85
150
–55 to 150
Units
V
A
V
V
V
ºC
ºC
ºC
THERMAL CHARACTERISTICS
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
4-layer PCB, based on JEDEC standard
Value Units
28
ºC/W
*Additional thermal information available on Allegro Web site.
5.5
5.0
Maximum Power Dissipation, P
D
(max)
Power Dissipation, P
D
(W)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
(R
θ
J
A
=
28
ºC
/W
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3984
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.1 uF
0.22 uF
VREG
ROSC
CP1
CP2
VDD
Current
Regulator
OSC
Charge
Pump
VCP
REF
DMOS Full Bridge
0.1 uF
VBB1
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
SENSE1
Gate
Drive
R
S1
VBB2
STEP
DIR
RESET
MS1
MS2
PWM Latch
Blanking
Mixed Decay
Translator
Control
Logic
DMOS Full Bridge
OUT2A
OUT2B
ENABLE
SLEEP
DAC
SENSE2
R
S2
V
REF
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3984
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS
1
at T
A
= 25°C, V
BB
= 35 V (unless otherwise noted)
Characteristics
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
Symbol
Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, I
OUT
= –1.5 A
Sink Driver, I
OUT
= 1.5 A
Source Diode, I
F
= –1.5 A
Sink Diode, I
F
= 1.5 A
f
PWM
< 50 kHz
Operating, outputs disabled
Sleep Mode
f
PWM
< 50 kHz
Outputs off
Sleep Mode
Min.
8
0
3.0
–
–
–
–
–
–
–
–
–
–
V
DD
0.7
V
IN
= V
DD
0.7
–
–20
–20
–
150
0.7
20
23
0
–3
–
–
–
100
–
–
2.35
0.05
Typ.
2
–
–
–
0.350
0.300
–
–
–
–
–
–
–
–
–
–
<1.0
<1.0
50
300
1
30
30
–
0
–
–
–
475
165
15
2.7
0.10
Max.
35
35
5.5
0.450
0.370
1.2
1.2
4
2
10
8
5
10
–
V
DD
0.3
20
20
–
500
1.3
40
37
4
3
±15
±5
±5
800
–
–
3
–
Units
V
V
V
Ω
Ω
V
V
mA
mA
μA
mA
mA
μA
V
V
μA
μA
kΩ
mV
μs
μs
μs
V
μA
%
%
%
ns
°C
°C
V
V
V
BB
V
DD
R
DSON
V
F
I
BB
Motor Supply Current
Logic Supply Current
Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select 2
Input Hysteresis
Blank Time
Fixed Off-Time
Reference Input Voltage Range
Reference Input Current
Current Trip-Level Error
3
Crossover Dead Time
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
I
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
MS2
V
HYS(IN)
t
BLANK
t
OFF
V
REF
I
REF
err
I
V
IN
= V
DD
0.3
OSC > 3 V
R
OSC
= 25 kΩ
V
REF
= 2 V,
%I
TripMAX
=
38.27%
V
REF
= 2 V,
%I
TripMAX
= 70.71%
V
REF
= 2 V,
%I
TripMAX
= 100.00%
t
DT
T
J
T
JHYS
UV
LO
UV
HYS
V
DD
rising
1
Negative current is defined as coming out of (sourcing from) the specified device pin.
2
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
3
err
individual units, within the specified maximum and minimum limits.
I
= (I
Trip
– I
Prog
)
⁄
I
Prog
, where I
Prog
= %I
TripMAX
I
TripMAX
.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3984
DMOS Microstepping Driver with Translator
t
A
t
B
STEP
t
C
MS1, MS2,
RESET, or DIR
t
D
Time Duration
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
Figure 1. Logic Interface Timing Diagram
Symbol
t
A
t
B
t
C
t
D
Typ.
1
1
200
200
Unit
μs
μs
ns
ns
Table 1. Microstep Resolution Truth Table
MS1
L
H
L
H
MS2
L
L
H
H
Microstep Resolution
Full Step
Half Step
Quarter Step
Sixteenth Step
Excitation Mode
2 Phase
1-2 Phase
W1-2 Phase
4W1-2 Phase
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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