7
0
R
QPro Virtex 2.5V QML
High-Reliability FPGAs
0
2
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
•
•
•
0.22
µm
5-layer metal process
100% factory tested
Available to Standard Microcircuit Drawings
-
-
-
-
5962-99572 for XQV300
5962-99573 for XQV600
5962-99574 for XQV1000
Contact Defense Supply Center Columbus (DSCC)
for more information at
http://www.dscc.dla.mil
Features
•
•
•
•
Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
Guaranteed over the full military temperature range
(–55°C to +125°C)
Ceramic and Plastic Packages
Fast, high-density Field-Programmable Gate Arrays
-
-
-
•
-
-
•
-
-
•
Densities from 100K to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
16 high-performance interface standards
Connects directly to ZBTRAM devices
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4K-bit
RAMs
Fast interfaces to external high-performance RAMs
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
Description
The QPro™ Virtex™ FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
exploiting an aggressive 5-layer-metal 0.22
µm
CMOS pro-
cess. These advances make QPro Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex family comprises the four members shown in
Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
Refer to the
“Virtex™ 2.5V Field Programmable Gate
Arrays”
commercial data sheet for more information on
device architecture and timing specifications.
Multi-standard SelectI/O™ interfaces
Built-in clock-management circuitry
Hierarchical memory system
-
-
-
•
Flexible architecture that balances speed and density
-
-
-
-
-
-
-
•
Supported by FPGA Foundation™ and Alliance
Development Systems
-
-
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Wide selection of PC and workstation platforms
Unlimited reprogrammability
Four programming modes
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
•
SRAM-based in-system configuration
-
-
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
QPro Virtex 2.5V QML High-Reliability FPGAs
Table 1:
QPro Virtex Field-Programmable Gate Array Family Members
Device
XQV100
XQV300
XQV600
XQV1000
System Gates
108,904
322,970
661,111
1,124,022
CLB Array
20 x 30
32 x 48
48 x 72
64 x 96
Logic Cells
2,700
6,912
15,552
27,648
Maximum
Available I/O
180
316
316
404
Block RAM Bits
40,960
65,536
98,304
131,072
Max Select
RAM Bits
38,400
98,304
221,184
393,216
R
Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol
V
CCINT
V
CCO
V
REF
V
IN(3)
V
TS
V
CC
T
STG
T
J
Supply voltage relative to GND
Supply voltage relative to GND
Input reference Voltage
Input voltage relative to GND
Using V
REF
Internal threshold
Voltage applied to 3-state output
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
Junction temperature
Ceramic packages
Plastic packages
Description
Min/Max
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
–65 to +150
+150
+125
Units
V
V
V
V
V
V
ms
°C
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. For protracted periods (e.g., longer than a day), V
IN
should not exceed V
CCO
by more that 3.6V.
2
www.xilinx.com
1-800-255-7778
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
R
QPro Virtex 2.5V QML High-Reliability FPGAs
Recommended Operating Conditions
Symbol
V
CCINT
V
CCO
T
IN
T
IC
Description
Supply voltage relative to GND, T
C
= –55°C to +125°C
Supply voltage relative to GND, T
J
= –55°C to +125°C
Supply voltage relative to GND, T
C
= –55°C to +125°C
Supply voltage relative to GND, T
J
= –55°C to +125°C
Input signal transition time
Initialization Temperature Range
(4)
XQVR300
XQVR600
XQVR1000
T
OC
Operational Temperature Range
(5)
XQVR300
XQVR600
XQVR1000
Ceramic packages
Plastic packages
Ceramic packages
Plastic packages
Min
2.5 – 5%
2.5 – 5%
1.2
1.2
-
–55
–55
–40
–55
–55
–55
Max
2.5 + 5%
2.5 + 5%
3.6
3.6
250
+125
+125
+125
+125
+125
+125
Units
V
V
V
V
ns
°C
°C
°C
°C
°C
°C
Notes:
1. Correct operation is guaranteed with a minimum V
CCINT
of 2.25V (Nominal V
CCINT
– 10%). Below the minimum value stated above,
all delay parameters increase by 3% for each 50 mV reduction in V
CCINT
below the specified range.
2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°
C.
3. Input and output measurement threshold is ~50% of V
CC
.
4. Initialization occurs from the moment of V
CC
ramp-up to the rising transition of the INIT pin.
5. The device is operational after the INIT pin has transitioned high.
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRIO
I
CCINTQ
Description
Data retention V
CCINT
voltage
(below which configuration data may be lost)
Data retention V
CCO
voltage
(below which configuration data may be lost)
Quiescent V
CCINT
supply current
(1)
Device
All
All
XQV100
XQV300
XQV600
XQV1000
I
CCOQ
Quiescent V
CCINT
supply current
(1)
XQV100
XQV300
XQV600
XQV1000
I
REF
I
L
C
IN
I
RPU
I
RPD
V
REF
current per V
REF
pin
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) at V
IN
= 0V, V
CCO
= 3.3V (sample tested)
Pad pull-down (when selected) at V
IN
= 3.6V (sample tested)
-
-
-
-
-
Min
2.0
1.2
-
-
-
-
-
-
-
-
-
–10
-
(2)
(2)
Max
-
-
50
75
100
100
2
2
2
2
20
+10
8
0.25
0.15
Units
V
V
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
pF
mA
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
QPro Virtex 2.5V QML High-Reliability FPGAs
R
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed output currents over
the recommended operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are
Input/Output
Standard
LVTTL
(1)
LVCMOS2
PCI, 3.3V
PCI, 5.0V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
AGP
V
IL
V, min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, max
0.8
0.7
44% V
CCINT
0.8
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V, min
2.0
1.7
60% V
CCINT
2.0
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
IH
V, max
5.5
5.5
V
CCO
+ 0.5
5.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
chosen to ensure that all standards meet their specifica-
tions. The selected standards are tested at minimum V
CCO
with the respective V
OL
and V
OH
voltage levels shown.
Other standards are sample tested.
V
OL
V, max
0.4
0.4
10% V
CCO
0.55
0.4
0.6
0.4
0.4
0.4
V
REF
– 0.6
V
REF
– 0.8
V
REF
– 0.65
V
REF
– 0.80
V
REF
– 0.4
10% V
CCO
V
OH
V, min
2.4
1.9
90% V
CCO
2.4
n/a
n/a
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.65
V
REF
+ 0.80
V
REF
+ 0.4
90% V
CCO
I
OL
mA
24
12
(2)
(2)
I
OH
mA
–24
–12
(2)
(2)
40
36
8
24
48
8
16
7.6
15.2
8
(2)
n/a
n/a
-8
–8
–8
–8
–16
–7.6
–15.2
–8
(2)
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
4
www.xilinx.com
1-800-255-7778
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
R
QPro Virtex 2.5V QML High-Reliability FPGAs
Virtex Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in
"IOB Input Switching Characteristics
Standard Adjustments" on page 6.
Speed Grade
-4
Symbol
Propagation Delays
Description
Device
Min
Max
Units
T
IOPI
T
IOPID
Pad to I output, no delay
Pad to I output, with delay
All
XQV100
XQV300
XQV600
XQV1000
-
-
-
-
-
-
-
-
-
-
1.0
1.9
1.9
2.3
2.7
2.0
4.8
5.1
5.5
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
IOPLI
T
IOPLID
Pad to output IQ via transparent latch, no
delay
Pad to output IQ via transparent latch, with
delay
All
XQV100
XQV300
XQV600
XQV1000
Sequential Delays
T
IOCKIQ
T
IOPICK
/ T
IOICKP
T
IOPICKD
/ T
IOICKPD
T
IOICECK
/ T
IOCKICE
T
IOSRCKI
/ T
IOCKISR
Set/Reset Delays
Clock CLK to output IQ
All
-
0.8
ns
Setup and Hold Times with Respect to Clock CLK
Setup Time / Hold Time
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
All
All
All
All
2.0 / 0
5.0 / 0
1.0 / 0
1.3 / 0
-
-
-
-
ns
ns
ns
ns
T
IOSRIQ
T
GSRQ
SR input to IQ (asynchronous)
GSR to output IQ
All
All
-
-
1.8
12.5
ns
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,
but if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
