SP705-708/813L
Low Power Microprocessor Supervisory Circuits
s
Precision Voltage Monitor:
SP705/707/813L at 4.65V
SP706/708 at 4.40V
s
RESET Pulse Width - 200ms
s
Independent Watchdog Timer - 1.6s
Timeout (SP705/706/813L)
s
60µA Maximum Supply Current
s
Debounced TTL/CMOS Manual Reset Input
s
RESET Asserted Down to V
CC
= 1.1V
s
Voltage Monitor for Power Failure or Low
Battery Warning
s
Available in 8-pin PDIP, NSOIC, and
Now available in Lead Free
µSOIC
packages
s
Pin Compatible Enhancement to Industry Standard 705-708/813L Series
s
Functionally Compatible to Industry Standard 1232 Series
DESCRIPTION…
The
SP705-708/813L
series is a family of microprocessor (µP) supervisory circuits that
integrate myriad components involved in discrete solutions which monitor power-supply and
battery in
µP
and digital systems. The
SP705-708/813L
series will significantly improve
system reliability and operational efficiency when compared to solutions obtained with discrete
components. The features of the
SP705-708/813L
series include a watchdog timer,
a
µP
reset, a Power Fail Comparator, and a manual-reset input. The
SP705-708/813L
series is ideal for applications in automotive systems, computers, controllers, and intelligent
instruments. The
SP705-708/813L
series is an ideal solution for systems in which critical
monitoring of the power supply to the
µP
and related digital components is demanded.
Part
Number
SP705
SP706
SP707
SP708
SP813L
RESET
Threshold
4.65 V
4.40 V
4.65 V
4.40 V
4.65 V
RESET
Active
LOW
LOW
LOW and HIGH
LOW and HIGH
HIGH
Manual
RESET
YES
YES
YES
YES
YES
Watchdog
YES
YES
NO
NO
YES
PFI
Accuracy
4%
4%
4%
4%
4%
June 2008 Rev C
SP705 Low Power Microprocessor Supervisory Circuits
© 2008
Exar
Corporation
1
ABSOLUTE MAXIMUM RATINGS
This is a stress rating only and functional operation
of the device at these or any other conditions above
those indicated in the operation sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect reliability and cause permanent
damage to the device.
V
cc .......................................................................................
-0.3V to +6.0V
All Other Inputs (Note 1) ......... -0.3V to (Vcc+0.3V)
Input Current:
V
cc .............................................................................................................
20mA
GND ............................................................ 20mA
Output Current (all outputs) ......................... 20mA
ESD Rating ..................................................... 4KV
Continuous Power Dissipation
Plastic DIP (derate 9.09mW/°C above +70°C)727mW
SO (derate 5.88mW/°C above +70°C) ...... 471mW
Mini SO (derate 4.10mW/°C above +70°C) 330mW
Storage Temperature Range ....... -65°C to +160°C
Lead Temperature (soldering, 10s) ............ +300°C
SPECIFICATIONS
V
CC
= 4.75V to 5.50V for SP705/707/813L, V
CC
= 4.50V to 5.50V for SP706/708, T
A
= T
MIN
to T
MAX
, unless otherwise noted, typical at 25
o
C.
PARAMETER
Operating Voltage Range, V
CC
Supply Current, I
SUPPLY
Reset Threshold
Reset Threshold Hysteresis
Reset Pulse Width, t
RS
RESET Output Voltage
MIN.
1.
1
TYP.
MAX.
5.5
UNITS
V
µA
V
mV
CONDITIONS
40
4.50
4.25
140
V
CC
-1.5
0.8
4.65
4.40
40
200
60
4.75
4.50
280
MR=V
CC
or Floating, WDI Floating
SP705, SP707, SP813L, Note 2
SP706, SP708, Note 2
Note 2
Note 2
Note 2
I
SOURCE
= 800
µA
I
SOURCE
=4
µ
A, V
CC
=1.1V
I
SINK
= 3.2mA
Vcc = 1.1V, I
SINK
= 50
µA
SP705, SP706, SP813L
V
IL
= 0.4V, V
IH
= 0.8XV
CC
SP705, SP706, SP813L
V
CC
= 5V
SP705, SP706, SP813L
WDI = V
CC
SP705, SP706, SP813L
WDI = 0V
ms
V
0.40
0.30
Watchdog Timeout Period, t
WD
WDI Pulse Width, t
WP
WDI Input Threshold,
LOW
HIGH
WDI Input Current
1.00
1
1.60
2.25
s
µs
0.8
3.5
30
-75
-20
75
V
µA
June 2008 Rev C
SP705 Low Power Microprocessor Supervisory Circuits
© 2008
Exar
Corporation
2
SPECIFICATIONS
V
CC
= 4.75V to 5.50V for SP705/707/813L,813M, V
CC
= 4.50V to 5.50V for SP706/708, T
A
= T
MIN
to T
MAX
, unless otherwise noted, typical at 25
o
C.
PARAMETER
WDO Output Voltage
MR Pull-Up Current
MR Pulse Width, t
MR
MR Input Threshold
LOW
HIGH
MR to Reset Out Delay, t
MD
PFI Input Threshold
PFI Input Current
PFO Output Voltage
MIN.
V
CC
-1.5
TYP.
MAX.
0.40
UNITS
V
µA
ns
CONDITIONS
I
SOURCE
=800
µA
I
SINK
=3.2mA
MR = 0V
100
150
250
600
0.8
2.0
250
1.20
-25.00
V
CC
-1.5
0.4
1.25
0.01
1.30
25.00
V
ns
V
nA
V
I
SOURCE
= 800
µA
I
SINK
= 3.2mA
Note 2
V
CC
= 5V
Note 1:
The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA.
Note 2:
Applies to both RESET in the SP705-SP708 and RESET in the SP707/708/813L/813M.
DIP and SOIC
µSOIC
MR 1
V
CC
2
GND 3
PFI 4
SP705
SP706
SP813L
8 WDO
7 RESET / RESET*
6
WDI
RESET / RESET* 1
WDO 2
MR 3
V
CC
4
SP705
SP706
SP813L
8 WDI
7 PFO
6
PFI
5 PFO
5 GND
MR 1
V
CC
2
GND 3
PFI 4
SP707
SP708
8 RESET
7 RESET
6
N.C.
RESET 1
RESET 2
MR 3
V
CC
4
SP707
SP708
8 N.C.
7 PFO
6
PFI
5 PFO
5 GND
* SP813L only
Figure 1. Pinouts
* SP813L only
June 2008 Rev C
SP705 Low Power Microprocessor Supervisory Circuits
© 2008
Exar
Corporation
3
PIN DESCRIPTION
NAME
FUNCTION
SP705/706
DIP/
SOIC
µSOIC
SP707/708
DIP/
SOIC
µSOIC
SP813L
DIP/
SOIC
µSOIC
MR
Manual Reset - This input triggers a reset pulse
when pulled below 0.8V. This active-LOW input
has an internal 250
µ
A pull-up current. It can be
driven from a TTL or CMOS logic line or shorted
to ground with a switch
+5V power supply
Ground reference for all signals
Power-Fail Input - When this voltage monitor input
is less than 1.25V, PFO goes LOW. Connect PFI
to ground or V
CC
when not in use.
Power-Fail Output - This output is HIGH until PFI
is less than 1.25V.
Watchdog Input - If this input remains HIGH or
LOW for 1.6s, the internal watchdog timer times
out and WDO goes LOW. Floating WDI or
connecting WDI to a high-impedance tri-state
buffer disables the watchdog feature. The internal
watchdog timer clears whenever RESET is
asserted, WDI is tri-stated, or whenever WDI sees
a rising or falling edge.
No Connect.
Active-LOW RESET Output - This output pulses
LOW for 200ms when triggered and stays LOW
whenever V
CC
is below the reset threshold (4.65V
for the SP705/707/813L and 4.40V for the
SP706/708). It remains LOW for 200ms after V
cc
rises above the reset threshold or MR goes from
LOW to HIGH. A watchdog timeout will not trigger
RESET unless WDO is connected to MR.
Watchdog Output - This output pulls LOW when
the internal watchdog timer finishes its 1.6s count
and does not go HIGH again until the watchdog is
cleared. WDO also goes LOW during low-line
conditions. Whenever V
CC
is below the reset
threshold, WDO stays LOW. However, unlike
RESET, WDO does not have a minimum pulse
width. As soon as V
CC
is above the reset
threshold, WDO goes HIGH with no delay.
Active-HIGH RESET Output - This output is the
complement of RESET. Whenever RESET is
HIGH, RESET is LOW, and vice versa. Note the
SP813L/813M has a reset output only.
1
3
1
3
1
3
V
CC
GND
PF I
2
3
4
4
5
6
2
3
4
4
5
6
2
3
4
4
5
6
PFO
5
7
5
7
5
7
WDI
6
8
-
-
6
8
N.C.
-
-
6
8
-
-
RESET
7
1
7
1
-
-
WDO
8
2
-
-
8
2
RESET
-
-
8
2
7
1
Table 1. Device Pin Description
June 2008 Rev C
SP705 Low Power Microprocessor Supervisory Circuits
© 2008
Exar
Corporation
4
WDI
V
CC
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
WDO
250µA
MR
TIMEBASE FOR
RESET AND
WATCHDOG
RESET
GENERATOR
RESET/RESET*
V
CC
4.65V
(4.40V for the SP706 and SP813M)
PFI
PFO
1.25V
SP705
SP706
SP813L
GND
* For the SP813L only
Figure 2. Internal Block Diagram for the SP705/706/813L
V
CC
RESET
250µA
MR
RESET
GENERATOR
RESET
V
CC
4.65V
(4.40V for the SP708)
PFI
PFO
1.25V
SP707
SP708
GND
Figure 3. Internal Block Diagram for the SP707/708
June 2008 Rev C
SP705 Low Power Microprocessor Supervisory Circuits
© 2008
Exar
Corporation
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
